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Full-Text Articles in Engineering

Trends. Thinking On Transportation Security, Ibpp Editor Jan 2003

Trends. Thinking On Transportation Security, Ibpp Editor

International Bulletin of Political Psychology

This Trends article discusses the necessity of gathering intelligence successfully to combat terrorism as it pertains to commerce.

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Process Design, Development, Fabrication And Verification Of A Cmos Technology For Rit, Jeremiah L. Hebding Jan 2003

Process Design, Development, Fabrication And Verification Of A Cmos Technology For Rit, Jeremiah L. Hebding

Journal of the Microelectronic Engineering Conference

The motivation in creation of the Strongarm process flow was to create a robust “enabling” process that was easy to manufacture. Optimum process conditions have been determined through extensive SUPREM simulation. Electrical examination using ATLAS software allowed for parameter extraction of the computer-generated devices. Modeling the extracted parameters with standard device physics equations allowed for a SPICE level-2 analysis that could be verified through electrical testing of actual fabricated devices. The technology was designed for a two micron, twin-well process incorporating a 4Onm gate oxide and an N+ poly gate. Source and drain implants are at 2E15 cm2, …

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Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp Jan 2003

Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp

Journal of the Microelectronic Engineering Conference

In this investigation, efforts have been made to move the Microelectronic Engineering Program at Rochester Institute of Technology to the next technology node by developing and fabricating a 0.5μm PMOS process. Currently, RIT is fabricating 1.0μm CMOS devices. A successful 0.5μm PMOS process can be incorporated into a full flow 0.5μm CMOS process. Both process and electrical simulations were done in order to predict performance. Key process features include blanket n-well, LOCOS isolation, 15nm gate oxide, i-line lithography, self-aligned source and drain, P+ doped polysilicon gates, and shallow source and drains. A test chip was created and the fabrication process …

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Spice Parameter Extraction From Simulations And Experimental Data, Robert L. Saxer Jr Jan 2003

Spice Parameter Extraction From Simulations And Experimental Data, Robert L. Saxer Jr

Journal of the Microelectronic Engineering Conference

SPICE parameters are a valuable tool used in the designing of integrated circuits. SPICE parameters communicate device behavior to circuit simulators. The purchase and support of Silvaco’s UTMOST software provided the function of extracting SPICE parameters from devices at RIT. With this new capability, RIT can obtain new levels of circuit simulation accuracy before fabrication. A method of SPICE parameter extraction was created and documented for simulated and experimental data.

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Design And Fabrication Of Finfets On Soi Substrates, Steven D. Kirby Jan 2003

Design And Fabrication Of Finfets On Soi Substrates, Steven D. Kirby

Journal of the Microelectronic Engineering Conference

A Fin Field Effect Transistor (FinFET) is one of several novel devices that may be used in the future to minimize short channel effects. The FinFET is fabricated on silicon on insulator (SOI) substrate and uses basic integrated circuit processing techniques to obtain a double gate structure. The double gate structure helps to improve subthreshold characteristics and provides low leakage current. The objective of this project was to improve the FinFET device built at RIT. Functioning FinFETs were designed and fabricated previously at RIT. The new design and process changes will help in the understanding of issues found in previous …

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On The Influence Of Surface Treatment On Electrical Characteristics Of Schottky Diodes, Donald J. Hamilton Jan 2003

On The Influence Of Surface Treatment On Electrical Characteristics Of Schottky Diodes, Donald J. Hamilton

Journal of the Microelectronic Engineering Conference

The effect of surface treatment on electrical characteristics of aluminum-silicon contacts has been observed. It has been shown that the electrical characteristics of the contacts are affected by the quality of the interfacial oxide and sintering conditions. Four different surface treatments were performed on the silicon prior to metal deposition to vary the thickness and quality of the interfacial oxide. Four different sintering conditions were performed on the wafers to determine the effect of temperature and ramp-down rates. Three methods of calculating barrier height were used: current-voltage, current-temperature, and capacitance-voltage. Some results correlated well with previous reported work, however other …

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Design, Simulation And Fabrication Of Insulated Gate Bipolar Transistors (Igbt), Tejas K. Jhaveri Jan 2003

Design, Simulation And Fabrication Of Insulated Gate Bipolar Transistors (Igbt), Tejas K. Jhaveri

Journal of the Microelectronic Engineering Conference

This project serves as a study to determine the feasibility of the current CMOS toolsets and processes available at Semiconductor & Microsystems Fabrication Laboratory (SMFL) for the fabrication of whole wafer power devices. Several designs and devices were explored. The Insulated Gate Bipolar Transistor (~LGBT) is a device widely used for high power electronic applications and was selected for this study. This device has bipolar current flow and a MOS gate thus combining advantages of both the Double diffused MOS (DMOS) and Power Bipolar junction transistor. Prototypes consisting of transistors with varying densities, gate lengths and gate widths were fabricated …

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Optically Injected Circuits In A 0.18 Μm Cmos, Gregory Ardault Jan 2003

Optically Injected Circuits In A 0.18 Μm Cmos, Gregory Ardault

Journal of the Microelectronic Engineering Conference

Power consumption and power conversion efficiency have been two key parameters characterizing the performance of electronic circuits since their dawn. With the increasing demand of miniaturization, mobility and portability of electronic industrial and consumer equipment, low-power and high-efficiency circuits are in high demand. Possible energy sources to enable mobility and/or portability are chemical (e.g. batteries, accumulators, micro gas, engine, fuel cells), mechanical (e.g. elastic energy in springs, vibrations, oscillations, ultrasound), thermal (e.g. body heat), EM-Field (e.g. inductive coupling, capacitive coupling, RF) and optical (photovoltaic cells). They are a great number of applications for which lowpower operation can be replaced with …

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Design And Testing Of Off Axis Illumination Filters For A 248nm Duv Exposure System, Matthew E. Malloy Jan 2003

Design And Testing Of Off Axis Illumination Filters For A 248nm Duv Exposure System, Matthew E. Malloy

Journal of the Microelectronic Engineering Conference

This study involves the design and testing of off axis illumination apertures for an ASML 5500/90 248nm DUV stepper. X and V slot pole apertures based on dipole theory were designed, fabricated out of aluminum, and inserted into the optical column of the stepper. Test patterns consisting of vertically oriented features were printed with and without dipole illumination, exposed, and compared to determine their effectiveness. As expected, features which were to small to print under standard illumination imaged exceptionally well using the x slot pole aperture. The y slot pole aperture delivered the same results as standard illumination which was …

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Printability And Line Edge Roughness Of Optical Proximity Correction Features, John Wittenzellner Jan 2003

Printability And Line Edge Roughness Of Optical Proximity Correction Features, John Wittenzellner

Journal of the Microelectronic Engineering Conference

Optical Proximity Correction (OPC) has been used for many years now in the semiconductor industry to provide through-pitch focus and dose matching across an entire mask field. By adding sub-resolution features, lines with large duty ratios can be made to have similar imaging properties as dense line patterns, reducing CD variation and increasing the flexibility of the design space. The subresolution features subtract zero-order diffraction energy which is the dominating determinate of how features are imaged in the resist. A binary chrome photomask with sub-resolution OPC features was designed at the Rochester Institute of Technology and fabricated by Photronics Inc. …

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Design, Fabrication, And Characterization Of An Alternating Phase Shifting Mask For Duv Lithography, Andrew C. Estroff Jan 2003

Design, Fabrication, And Characterization Of An Alternating Phase Shifting Mask For Duv Lithography, Andrew C. Estroff

Journal of the Microelectronic Engineering Conference

The goal of this project is to design, fabricate, and characterize alternating phase shift masks for 248nm DUV lithography. The characterization of the masks was to include etch depth and sidewall angle measurements via atomic force microscopy (AFM). Etch times were to be varied in order to induce phase changes of 900, 1800, and 270°; one binary chrome on glass mask was also supposed to be fabricated to show the enhancements offered in processing by the phase shifting masks. The measurements of the etch profiles should not only be useful in determining the achieved phase shift and their correlation to …

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Investigation Of Undercut On Alternating Aperture Phase Shift Mask, Marc J. Cangemi Jan 2003

Investigation Of Undercut On Alternating Aperture Phase Shift Mask, Marc J. Cangemi

Journal of the Microelectronic Engineering Conference

Each new technology node tests the limits of optical Lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase-shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photomask can increase the resolution of a lithographic image significantly. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is to undercut the chrome or retract the …

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Phase Edge Contact Immersion Lithography At 193 Nm, Bryan P. Watson Jan 2003

Phase Edge Contact Immersion Lithography At 193 Nm, Bryan P. Watson

Journal of the Microelectronic Engineering Conference

A phase-edge contact immersion optical lithography system utilizing a 193nm Argon Fluoride (ArF) excimer laser was designed. The ArF laser was passed through a 600nm quartz diffraction grating. The diffraction grating was placed in contact with the substrate. The gap between the mask and substrate was varied by the use of transparency sheets to study the effects of linewidth control and resolution as a function of this distance. This was done for both air and water as the indexing medium between the mask and substrate. Images were acquired from scanning electron micrographs (SEM’s) for each of the cases analyzed.

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Tisi2 And Cosi2 Silicide Formation Using N2+ Implant, Christine Larson Jan 2003

Tisi2 And Cosi2 Silicide Formation Using N2+ Implant, Christine Larson

Journal of the Microelectronic Engineering Conference

Suicides have been used in industry since minimum dimensions reached the 1 ~tm node. The goal of this project is to explore Titanium and Cobalt Silicide and incorporate its use into the JUT sub-micron CMOS process. TiSi2 had been the industry standard to decrease this resistivity through the 0.25μm node. The current industry standard is CoSi2, with resistivity independent of its grain size. This allows for the smaller dimensions. However, CoSi2 formation is very sensitive to oxygen contamination. A Ti capping layer may minimize the contamination by reacting with any oxygen. The nitrogen implant prior to …

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Study Of Nickel Silicide Processes For Advanced Cmos Applications, Branislav Curanovic Jan 2003

Study Of Nickel Silicide Processes For Advanced Cmos Applications, Branislav Curanovic

Journal of the Microelectronic Engineering Conference

A study has been performed to determine critical mechanisms involved in formation of nickel suicides. The process parameters under investigation were silicidation temperature, presilicide N2+ implant, and the presence of a titanium capping layer. Contact sheet resistance phosphorous-implanted silicon was measured and determined to degrade with high silicidation temperature. Titanium capping was found to improve contact resistance and compensate for the effects of high temperature treatment for polycides. The nitrogen incorporation via implant shows a degradation in resistivity for both silicides and polycides.

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Development Of A Polycrystalline Si1-Xgex Gate Material By Lpcvd/Pvd, Michael C. Mattioli Jan 2003

Development Of A Polycrystalline Si1-Xgex Gate Material By Lpcvd/Pvd, Michael C. Mattioli

Journal of the Microelectronic Engineering Conference

Polycrystalline Si1-xGex (poly Si-Ge) was explored as a process compatible alternative gate material for PMOS transistors at RIT. This material has been previously shown to exhibit several favorable characteristics when used as a gate material for PMOS transistors. Benefits include the ability to engineer the workfunction, improved dopant activation for reduced gate depletion effects, and reduced boron encroachment. A process by which poly Si-Ge could be integrated as a gate material into the RIT submicron CMOS process was developed by alternating polycrystalline silicon deposition by LPCVD and the application of germanium by PVD. The effects on physical …

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Simulation And Modeling Of A Vertical Pmos Transistor, Mufadal Arubali Jan 2003

Simulation And Modeling Of A Vertical Pmos Transistor, Mufadal Arubali

Journal of the Microelectronic Engineering Conference

Conventional planar CMOS scaling is able to achieve the traditional 17% performance gain for generation to generation. Planar CMOS scaling will soon encounter a “red-zone” at 65nm node or lower as we proceed towards the road map. As a result, the industry is likely to adopt a non-planar, fully depleted structure of various geometries including finFET, double-gate planar MOSFETs and vertical MOSFETs that are being investigated. This study focuses on Silvaco simulation and modeling of vertical P-type MOSFETs. The goal of this project was to determine whether Silvaco adequately, models degenerate doping levels (e.g. delta doped region) to minimize the …

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Design And Fabrication Of Giant Mangnetoresistance (Gmr) Spin-Value Structures, Dilipkumar Mahenthiran Jan 2003

Design And Fabrication Of Giant Mangnetoresistance (Gmr) Spin-Value Structures, Dilipkumar Mahenthiran

Journal of the Microelectronic Engineering Conference

GMR Spin-Valve test structures have been fabricated in collaboration with Veeco/CVC. Various multi-layer spin-valve structures such as synthetic metal spin-valve, bottom nano oxide layer (BNOL) spin-valve, top nano oxide layer (TNOL) spin-value and surfactant spin-value structures were deposited utilizing Veeco’s UHV Nexus PVD-10 Target Planetary system. The test structures were designed by using Mentor Graphics CAD tool. Photo masks were fabricated by using Perkin Elmer MEBES III electron beam writer. A photolithographic process consisting of etch and lift-off steps has been developed to define the dimensions of the spin valve test structure. The electrical and magnetic properties of sheet film …

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Design And Fabrication Of A Micro-Bearing Assembly To Study Rotor Friction, Daniel W. Brown Jan 2003

Design And Fabrication Of A Micro-Bearing Assembly To Study Rotor Friction, Daniel W. Brown

Journal of the Microelectronic Engineering Conference

The objective of this investigation was to design and fabricate a metrology tool for measuring the wear in micro-bearings. The critical component of the tool was a silicon test bed consisting of a bearing shaft and a set of microchannels to direct an air stream onto the fins of a micro-rotor assembled onto the bearing shaft. By driving the micro-rotor pneumatically, surface interactions between the bearing and the rotor can be studied over time. The silicon test bed mates to a custom aluminum chuck which has provisions for sealing the test bed and supplying air pressure from an external source. …

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Characterization Of Epitaxial Layer Stacking Faults, Alexa M. Perry Jan 2003

Characterization Of Epitaxial Layer Stacking Faults, Alexa M. Perry

Journal of the Microelectronic Engineering Conference

As device geometries shrink and customer demands for more stringent zero-defect imagers increases, epitaxy growth is becoming an increasingly critical procedure in microelectronic processing. Therefore, the defects manifested by the epi growth are also an important concern. More specifically, epitaxial layer stacking faults can be detrimental to device performance and, in the case of image sensor devices, they have been shown to cause bright pixels and bright columns in the dark field. Assisting the Image Sensor Solutions Division of Eastman Kodak Company, the ability to screen and monitor incoming silicon has been accomplished and assessed using an unpatterned wafer particle …

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Gate Oxide Characterizations For Non-Planar Cmos, Keith H. Tabakman Jan 2003

Gate Oxide Characterizations For Non-Planar Cmos, Keith H. Tabakman

Journal of the Microelectronic Engineering Conference

The objective of this investigation was to characterize oxides grown on the sidewalls of etched silicon profiles. Conventional CMOS process technologies were used to fabricate vertical sidewall capacitors in addition to planar ones. Sidewall oxidation is a cornerstone in the development of non-planar CMOS devices such as the finFET and Vertical MOSFETs. The quality of this oxide is extremely important, even more so as devices are scaled such that oxide thicknesses are on the order of a few atomic layers. In order to obtain insight into the characteristics of these emerging devices, the effects of a non-planar gate oxidation must …

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Process Metrology For Ultrathin Gate Dielectrics, Julien Buisson Jan 2003

Process Metrology For Ultrathin Gate Dielectrics, Julien Buisson

Journal of the Microelectronic Engineering Conference

One of the major challenges is to be able to grow and accurately measure such thicknesses of gate oxides. In addition, the gate oxide thickness may change during the polysilicon deposition, which is important to measure from the device point of view. The use of variable angle spectroscopic ellipsometer (VASE) has been shown to provide a technique for directly measuring the thickness of the oxide underneath polysilicon. The objective of this study Is to use VASE (energy range from 0.78 eV to 6 eV, which corresponds to wavelengths from 200 to 1600 nm) to measure ultra thin silicon dioxide layers …

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Analysis And Modeling Of Polysilicon Critical Dimensions, Jasper P. Munson Jan 2003

Analysis And Modeling Of Polysilicon Critical Dimensions, Jasper P. Munson

Journal of the Microelectronic Engineering Conference

The objective of the project was to evaluate polysilicon CD etch bias as it was affected by etch time, measurement feature within the exposure field, and the product being measured. Characterization of the trends has generated a summarizing model that uses etch time, measurement feature, and product type as significant factors in determining polysilicon CD etch bias. Etch time was found to be a continuous factor, while measurement site and product type were categorical. Measurement Site A was found to be independent of measurement Site B, independent of Site C, etc., as well as Product 1 was found independent of …

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Effective Generation Lifetime (Τg,Eff) And Surface Generation Velocity (Seff) Extractions Via Zerbst Plot Analysis, Sylvain Garaud Jan 2003

Effective Generation Lifetime (Τg,Eff) And Surface Generation Velocity (Seff) Extractions Via Zerbst Plot Analysis, Sylvain Garaud

Journal of the Microelectronic Engineering Conference

Capacitance vs. time (c-t) characteristics of a MOS structure show the capacitance change after a pulse bias is applied which drives the structure first into accumulation then into deep inversion. Since the time constant of minority carrier generation is relatively long, the MOS structure requires time to reach equilibrium after the pulse bias is applied. Immediately after the pulse bias is applied, the depletion layer extends more widely then the depletion layer becomes narrower - the MOS structure approaches equilibrium as more and more minority carriers are generated. Finally, the depletion layer reaches its equilibrium width. This proves charge neutrality. …

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Auger Electron Spectroscopy Calibration, Michael David Fattu Jan 2003

Auger Electron Spectroscopy Calibration, Michael David Fattu

Journal of the Microelectronic Engineering Conference

This study presents a brief introduction to Auger Spectroscopy with experimental results taken from a spectrometer donated by Kodak in 2000. The tool has been calibrated using materials with high electron energy signals, primarily Titanium and Gold. Analysis of thin film spectra include the materials Aluminum, Gold, Si~N4, Germanium, and Tungsten. Depth profile measurements were made using a groove-etch technique and ion bombardment sputtering of a multi-layer metal stack. Future work will involve enabling x-Ray spectroscopy capabilities of the tool and increasing sensitivity of measurements.

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Advancing Rit To Submicron Technology: Design And Fabrication Of 0.5Μm N-Channel Mos Transistors, Michael Aquilino Jan 2003

Advancing Rit To Submicron Technology: Design And Fabrication Of 0.5Μm N-Channel Mos Transistors, Michael Aquilino

Journal of the Microelectronic Engineering Conference

The design and fabrication of N-channel MOS transistors with effective gate lengths of 0.5μm or smaller have been completed at the Semiconductor and Microsystems Fabrication Laboratory at the Rochester Institute of Technology. An NMOS device with Lmask = 0.7μm results in an Leff= 0.5μm. The drive current for this device with supply voltage of 3.5V is 108μA/μm. The sub-threshold slope is 100mV/decade and a DIBL parameter of 29mV/V is reported. An NMOS device withLmask=0.6μm results in an Leff =0.4μm. The drive current for this device with supply voltage of 3.5V is l40μA/μm. The sub-threshold …

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Ole Miss Engineer 2003 Jan 2003

Ole Miss Engineer 2003

Ole Miss Engineer

No abstract provided.

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Investigation On How To Improve Latent Semantic Analysis Performance, Thao Doan Jan 2003

Investigation On How To Improve Latent Semantic Analysis Performance, Thao Doan

Inquiry: The University of Arkansas Undergraduate Research Journal

Latent Semantic Analysis (LSA) is a matching technique capable of recognizing the semantic relationships of data that ordinary techniques such as string matching cannot. This is especially valuable for data integration applications, like those of Acxiom, where data items are usually related by context, rather than in a literal match. Even though it has been shown that LSA is 30% more effective in finding and ranking relevant pieces of information than existing string-by-string matching techniques (Deerwester et al., 1990; Dumais, 1995), the performance of the LSA seems to be affected by the presence of shared words, or “noise”, in data. …

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Parametrically Tunable Audio Shelving And Equalizing Ladder Wave Digital Filters, S. A. Samad Jan 2003

Parametrically Tunable Audio Shelving And Equalizing Ladder Wave Digital Filters, S. A. Samad

Turkish Journal of Electrical Engineering and Computer Sciences

Parametrically tunable audio equalizers are conventionally realized using allpass digital filter networks. They consist of first-order shelving filters and second-order equalizing filters. In this paper, ladder wave digital filters (WDFs) with parametrically tunable coefficients are proposed as shelving and equalizing filters. Similar to the allpass realization, the transfer function power complementary property of WDFs is used to obtain efficient shelving and equalizing filters. However, unlike the allpass structures, the transfer function and the tunable parameters of the ladder WDF are derived from the analog filter equivalent of the digital shelving and equalizing filters. For the shelving WDF, the cut-off frequency …

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Computer Modeling Of Tornado Forces On A Cubic Building Using Large Eddy Simulation, R. Panneer Selvam, Paul C. Millett Jan 2003

Computer Modeling Of Tornado Forces On A Cubic Building Using Large Eddy Simulation, R. Panneer Selvam, Paul C. Millett

Journal of the Arkansas Academy of Science

A tornado changes its wind speed and direction rapidly; therefore, it is difficult to study the effects of a tornado on buildings in a wind tunnel. The status of the tornado-structure interaction and various models of the tornado wind field found in literature are surveyed. Three dimensional computer modeling work using the turbulence model based on large eddy simulation is presented. The effect of a tornado on a cubic building is considered for this study. The Navier-Stokes (NS) equations are approximated by the finite difference method and solved by an implicit procedure. The force coefficients are plotted in time to …

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