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Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Machine Learning Applications To Static Timing Analysis, Waseem Mohamed Raslan Jun 2022

Machine Learning Applications To Static Timing Analysis, Waseem Mohamed Raslan

Theses and Dissertations

Modeling complex cell behavior is critical for accurate static timing analysis. Effective current source model, ECSM, and composite current source, CCS, waveform data compression became a necessity to reduce the size of technology files and increase the accuracy of the cell characterization data. We used deep learning nonlinear Autoencoders to compress voltage and current waveforms and compared them with singular value decomposition, SVD, approach. Autoencoders gave ~1.67x compression ratio for voltage waveforms better than SVD approach and gave 45x to 55x better compression ratio compared to other lossless techniques like bz2 and gzip. Autoencoders achieved ~1.7x compression ratio for complex …


Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning And Its Application To Layout Optimization, Mohamed Saleh Abouelyazid Saleh May 2022

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning And Its Application To Layout Optimization, Mohamed Saleh Abouelyazid Saleh

Theses and Dissertations

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (< 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts.

This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. …


Single Event Transient Sensitivity Measurement And Worst-Case Test Vector Exploration For Asic Devices Exposed To Space Single Event Environment, Mohamed Wael Jan 2022

Single Event Transient Sensitivity Measurement And Worst-Case Test Vector Exploration For Asic Devices Exposed To Space Single Event Environment, Mohamed Wael

Theses and Dissertations

Space radiation and nuclear reactors produce single event effects (SEE) in electronic circuits and impact their performance. The SEE phenomena cause circuits and electronic devices to fail by producing faulty results. Therefore, today’s circuit’s reliability is a significant concern for all circuit designers.

This thesis suggests a new automated flow to measure the single-event-transient (SET) effects in combinational circuits in application-specific integrated circuits (ASIC) while reaching full fault coverage. The developed flow characterizes the whole circuit nodes by identifying the most sensitive paths to the propagated SET pulses from the node under test to an observable primary output, causing single …


Fault Modeling And Test Vector Generation For Asic Devices Exposed To Space Single Event Environment, Ahmed Mohamed May 2021

Fault Modeling And Test Vector Generation For Asic Devices Exposed To Space Single Event Environment, Ahmed Mohamed

Theses and Dissertations

This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial …