Electrical and Electronics Commons^™

Low Power Multi-Channel Interface For Charge Based Tactile Sensors, Samuel Hansen

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

Analog front end electronics are designed in 65 nm CMOS technology to process charge pulses arriving from a tactile sensor array. This is accomplished through the use of charge sensitive amplifiers and discrete time filters with tunable clock signals located in each of the analog front ends. Sensors were emulated using Gaussian pulses during simulation. The digital side of the system uses SAR (successive approximation register) ADCs for sampling of the processed sensor signals.

Adviser: Sina Balkır

Design And Characterization Of Standard Cell Library Using Finfets, Phanindra Datta Sadhu

Master's Theses

The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the transistor's breakdown caused by short channel effects. An alternative solution to this is the FinFET transistor technology, where the gate of the transistor is a three dimensional fin that surrounds the transistor and prevents the breakdown caused by scaling …

Design, Analysis, And Simulation Of A Jitter Reduction Circuit (Jrc) System At 1ghz, Run Bin Yu

Master's Theses

The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the clock edge, could undermine the overall performance or even cause failures on the system. Deterministic jitter could be reduced during the designing process however random jitter during operation is somehow less-controllable and unavoidable. Being able to remove jitter on the clock would therefore play a vital role in system performance improvement.

This thesis implements a 1GHz fully feedforward jitter reduction circuit (JRC) which can be used as an on-chip IP core at clock tree terminals to …

Delay Extraction Based Equivalent Elmore Model For Rlc On-Chip Interconnects, Shamsul Arefin Siddiqui

Electronic Thesis and Dissertation Repository

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed …

Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.