Electrical and Electronics Commons^™

Demand-Side Load Management Using Single-Phase Residential Static Var Compensators, Muhammad Kamran Latif

Boise State University Theses and Dissertations

Distribution systems are going through a structural transformation from being radially-operated simple systems to becoming more complex networks to operate in the presence of the distributed energy resources (DERs) with significant levels of penetration. It is predicted that the share of electricity generation from DERs will keep increasing as the world is moving away from the power generation involving carbon-emission and towards cleaner energy sources such as solar, wind, and biofuels. However, the unstable behavior of the renewables resources presents challenges to the already existing distribution systems. One such problem is when the distribution feeder experience variable power supply due …

Real-Time Fault Detection And Reconfiguration Of A Three-Phase Electric Motor Drive, Danyal Mohammadi

Boise State University Theses and Dissertations

Variable-frequency drives (VFDs) are widely used for control of electrical machines such as induction motors (IMs) or permanent-magnet synchronous motors (PMSMs). Similar to other electrical devices, these drives are subject to failure. Several types of faults are associated with VFDs. For instance, faults such as an open-switch fault, a short-circuit switch fault are the two common faults in VFDs. These faults can yield catastrophic consequences if proper remedial action is not taken.

A unique remedial topology for the post-fault period and a new pulse width modulation (PWM) strategy are proposed so that not only the motor drive can continue the …

Hexarray: A Novel Self-Reconfigurable Hardware System, Fady Hussein

Boise State University Theses and Dissertations

Evolvable hardware (EHW) is a powerful autonomous system for adapting and finding solutions within a changing environment. EHW consists of two main components: a reconfigurable hardware core and an evolutionary algorithm. The majority of prior research focuses on improving either the reconfigurable hardware or the evolutionary algorithm in place, but not both. Thus, current implementations suffer from being application oriented and having slow reconfiguration times, low efficiencies, and less routing flexibility. In this work, a novel evolvable hardware platform is proposed that combines a novel reconfigurable hardware core and a novel evolutionary algorithm.

The proposed reconfigurable hardware core is a …

Integrated Circuit Design For Hybrid Optoelectronic Interconnects, Kehan Zhu

Boise State University Theses and Dissertations

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool.

Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible.

The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link …

High-Speed Delta-Sigma Data Converters For Next-Generation Wireless Communication, Sakkarapani Balagopal

Boise State University Theses and Dissertations

In recent years, Continuous-time Delta-Sigma(CT-ΔΣ) analog-to-digital converters (ADCs) have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths greater than 15 MHz and higher resolution of 10 to 14 bits. This dissertation investigates the current state-of-the-art high-speed single-bit and multi-bit Continuous-time Delta-Sigma modulator (CT-ΔΣM) designs and their limitations due to circuit non-idealities in achieving the performance required for next-generation wireless standards. Also, we presented complete architectural and circuit details of a high-speed single-bit and multi-bit CT-ΔΣM operating at a sampling rate of 1.25 GSps and 640 MSps respectively (the highest reported sampling rate in a 0.13 …