Computer and Systems Architecture Commons^™

Protecting Return Address Integrity For Risc-V Via Pointer Authentication, Yuhe Zhao

Masters Theses

Embedded systems based on lightweight microprocessors are becoming more prevalent in various applications. However, the security of them remains a significant challenge due to the limited resources and exposure to external threats. Especially, some of these devices store sensitive data and control critical devices, making them high-value targets for attackers. Software security is particularly important because attackers can easily access these devices on the internet and obtain control of them by injecting malware.

Return address (RA) hijacking is a common software attack technique used to compromise control flow integrity (CFI) by manipulating memory, such as return-to-libc attacks. Several methods have …

Securing Edge Computing: A Hierarchical Iot Service Framework, Sajan Poudel, Nishar Miya, Rasib Khan

Posters-at-the-Capitol

Title: Securing Edge Computing: A Hierarchical IoT Service Framework

Authors: Nishar Miya, Sajan Poudel, Faculty Advisor: Rasib Khan, Ph.D.

Department: School of Computing and Analytics, College of Informatics, Northern Kentucky University

Abstract:

Edge computing, a paradigm shift in data processing, faces a critical challenge: ensuring security in a landscape marked by decentralization, distributed nodes, and a myriad of devices. These factors make traditional security measures inadequate, as they cannot effectively address the unique vulnerabilities of edge environments. Our research introduces a hierarchical framework that excels in securing IoT-based edge services against these inherent risks.

Our secure by design approach prioritizes …

Reinventing Integrated Photonic Devices And Circuits For High Performance Communication And Computing Applications, Venkata Sai Praneeth Karempudi

Theses and Dissertations--Electrical and Computer Engineering

The long-standing technological pillars for computing systems evolution, namely Moore's law and Von Neumann architecture, are breaking down under the pressure of meeting the capacity and energy efficiency demands of computing and communication architectures that are designed to process modern data-centric applications related to Artificial Intelligence (AI), Big Data, and Internet-of-Things (IoT). In response, both industry and academia have turned to 'more-than-Moore' technologies for realizing hardware architectures for communication and computing. Fortunately, Silicon Photonics (SiPh) has emerged as one highly promising ‘more-than-Moore’ technology. Recent progress has enabled SiPh-based interconnects to outperform traditional electrical interconnects, offering advantages like high bandwidth density, …

Enhancing Accident Investigation Using Traffic Cctv Footage, Aksharapriya Peddi

Electronic Theses, Projects, and Dissertations

This Culminating Experience Project investigated how the densenet-161 model will perform on accident severity prediction compared to proposed methods. The research questions are: (Q1) What is the impact of usage of augmentation techniques on imbalanced datasets? (Q2) How will the hyper parameter tuning affect the model performance? (Q3) How effective is the proposed model compared to existing work? The findings are: Q1. The effectiveness of our model depends on the implementation of augmentation techniques that pay attention to handling imbalanced datasets. Our dataset poses a challenge due to distribution of classes in terms of accident severity. To address this challenge …

Deep Learning Frameworks For Accelerated Magnetic Resonance Image Reconstruction Without Ground Truths, Ibsa Kumara Jalata

Graduate Theses and Dissertations

Magnetic Resonance Imaging (MRI) is typically a slow process because of its sequential data acquisition. To speed up this process, MR acquisition is often accelerated by undersampling k-space signals and solving an ill-posed problem through a constrained optimization process. Image reconstruction from under-sampled data is posed as an inverse problem in traditional model-based learning paradigms. While traditional methods use image priors as constraints, modern deep learning methods use supervised learning with ground truth images to learn image features and priors. However, in some cases, ground truth images are not available, making supervised learning impractical. Recent data-centric learning frameworks such as …

Trojan Detection Expansion Of Structural Checking, Zachary Chapman

Graduate Theses and Dissertations

With the growth of the integrated circuit (IC) market, there has also been a rise in demand for third-party soft intellectual properties (IPs). However, the growing use of such Ips makes it easier for adversaries to hide malicious code, like hardware Trojans, into these designs. Unlike software Trojan detection, hardware Trojan detection is still an active research area. One proposed approach to this problem is the Structural Checking tool, which can detect hardware Trojans using two methodologies. The first method is a matching process, which takes an unknown design and attempts to determine if it might contain a Trojan by …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Classification Of Large Scale Fish Dataset By Deep Neural Networks, Priyanka Adapa

Electronic Theses, Projects, and Dissertations

The development of robust and efficient fish classification systems has become essential to preventing the rapid depletion of aquatic resources and building conservation strategies. A deep learning approach is proposed here for the automated classification of fish species from underwater images. The proposed methodology leverages state-of-the-art deep neural networks by applying the compact convolutional transformer (CCT) architecture, which is famous for faster training and lower computational cost. In CCT, data augmentation techniques are employed to enhance the variability of the training data, reducing overfitting and improving generalization. The preliminary outcomes of our proposed method demonstrate a promising accuracy level of …

Sel4 On Risc-V - Developing High Assurance Platforms With Modular Open-Source Architectures, Michael A. Doran Jr

Masters Theses

Virtualization is now becoming an industry standard for modern embedded systems. Modern embedded systems can now support multiple applications on a single hardware platform while meeting power and cost requirements. Virtualization on an embedded system is achieved through the design of the hardware-software interface. Instruction set architecture, ISA, defines the hardware-software interface for an embedded system. At the hardware level the ISA, provides extensions to support virtualization.

In addition to an ISA that supports hypervisor extensions it is equally important to provide a hypervisor completely capable of exploiting the benefits of virtualization for securing modern embedded systems. Currently there does …

Digital Simulations Of Memristors Towards Integration With Reconfigurable Computing, Ivris Raymond

Computer Science and Computer Engineering Undergraduate Honors Theses

The end of Moore’s Law has been predicted for decades. Demand for increased parallel computational performance has been increased by improvements in machine learning. This past decade has demonstrated the ever-increasing creativity and effort necessary to extract scaling improvements in CMOS fabrication processes. However, CMOS scaling is nearing its fundamental physical limits. A viable path for increasing performance is to break the von Neumann bottleneck. In-memory computing using emerging memory technologies (e.g. ReRam, STT, MRAM) offers a potential path beyond the end of Moore’s Law. However, there is currently very little support from industry tools for designers wishing to incorporate …

Chatgpt As Metamorphosis Designer For The Future Of Artificial Intelligence (Ai): A Conceptual Investigation, Amarjit Kumar Singh (Library Assistant), Dr. Pankaj Mathur (Deputy Librarian)

Library Philosophy and Practice (e-journal)

Abstract

Purpose: The purpose of this research paper is to explore ChatGPT’s potential as an innovative designer tool for the future development of artificial intelligence. Specifically, this conceptual investigation aims to analyze ChatGPT’s capabilities as a tool for designing and developing near about human intelligent systems for futuristic used and developed in the field of Artificial Intelligence (AI). Also with the helps of this paper, researchers are analyzed the strengths and weaknesses of ChatGPT as a tool, and identify possible areas for improvement in its development and implementation. This investigation focused on the various features and functions of ChatGPT that …

Wifi Sensing At The Edge Towards Scalable On-Device Wireless Sensing Systems, Steven M. Hernandez

Theses and Dissertations

WiFi sensing offers a powerful method for tracking physical activities using the radio-frequency signals already found throughout our homes and offices. This novel sensing modality offers continuous and non-intrusive activity tracking since sensing can be performed (i) without requiring wearable sensors, (ii) outside the line-of-sight, and even (iii) through the wall. Furthermore, WiFi has become a ubiquitous technology in our computers, our smartphones, and even in low-cost Internet of Things devices. In this work, we consider how the ubiquity of these low-cost WiFi devices offer an unparalleled opportunity for improving the scalability of wireless sensing systems. Thus far, WiFi sensing …

Small Business Office Network, Michael Gerome

Williams Honors College, Honors Research Projects

This project will emulate a small office network environment. The project will demonstrate the process of building and configuring the network to meet the requirements laid out in the project plan. This network includes four subnets with Windows 10 end devices and a Kali Linux device, it also includes five Cisco layer 2 switches and three Cisco routers. There are also three subnets connecting the routers to each other to enable routing between the subnets. After the network environment is set up, various penetration tests are performed from the Kali Linux device to gather information. The Nmap reconnaissance tool is …

Small Voip-Supported Network, Drina Hobson

Williams Honors College, Honors Research Projects

Create a small VoIP network using SIP using physical Cisco equipment. Implement advanced VoIP features such as multicast paging, voice message system & message waiting indicator, and music-on-hold.

Towards Multipronged On-Chip Memory And Data Protection From Verification To Design And Test, Senwen Kan, Jennifer Dworak

Computer Science and Engineering Theses and Dissertations

Modern System on Chips (SoCs) generally include embedded memories, and these memories may be vulnerable to malicious attacks such as hardware trojan horses (HTHs), test access port exploitation, and malicious software. This dissertation contributes verification as well as design obfuscation solutions aimed at design level detection of memory HTH circuits as well as obfuscation to prevent HTH triggering for embedded memory during functional operation. For malicious attack vectors stemming from test/debug interfaces, this dissertation presents novel solutions that enhance design verification and securitization of an IJTAG based test access interface. Such solutions can enhance SoC protection by preventing memory test …

Applying Hls To Fpga Data Preprocessing In The Advanced Particle-Astrophysics Telescope, Meagan Konst

McKelvey School of Engineering Theses & Dissertations

The Advanced Particle-astrophysics Telescope (APT) and its preliminary iteration the Antarctic Demonstrator for APT (ADAPT) are highly collaborative projects that seek to capture gamma-ray emissions. Along with dark matter and ultra-heavy cosmic ray nuclei measurements, APT will provide sub-degree localization and polarization measurements for gamma-ray transients. This will allow for devices on Earth to point to the direction from which the gamma-ray transients originated in order to collect additional data. The data collection process is as follows. A scintillation occurs and is detected by the wavelength-shifting fibers. This signal is then read by an ASIC and stored in an ADC …

Towards Qos-Based Embedded Machine Learning, Tom Springer, Erik Linstead, Peiyi Zhao, Chelsea Parlett-Pelleriti

Engineering Faculty Articles and Research

Due to various breakthroughs and advancements in machine learning and computer architectures, machine learning models are beginning to proliferate through embedded platforms. Some of these machine learning models cover a range of applications including computer vision, speech recognition, healthcare efficiency, industrial IoT, robotics and many more. However, there is a critical limitation in implementing ML algorithms efficiently on embedded platforms: the computational and memory expense of many machine learning models can make them unsuitable in resource-constrained environments. Therefore, to efficiently implement these memory-intensive and computationally expensive algorithms in an embedded computing environment, innovative resource management techniques are required at the …

A Memory-Centric Customizable Domain-Specific Fpga Overlay For Accelerating Machine Learning Applications, Atiyehsadat Panahi

Graduate Theses and Dissertations

Low latency inferencing is of paramount importance to a wide range of real time and userfacing Machine Learning (ML) applications. Field Programmable Gate Arrays (FPGAs) offer unique advantages in delivering low latency as well as energy efficient accelertors for low latency inferencing. Unfortunately, creating machine learning accelerators in FPGAs is not easy, requiring the use of vendor specific CAD tools and low level digital and hardware microarchitecture design knowledge that the majority of ML researchers do not possess. The continued refinement of High Level Synthesis (HLS) tools can reduce but not eliminate the need for hardware-specific design knowledge. The designs …

Improving The Programmability Of Networked Energy Systems, Noman Bashir

Doctoral Dissertations

Global warming and climate change have underscored the need for designing sustainable energy systems. Sustainable energy systems, e.g., smart grids, green data centers, differ from the traditional systems in significant ways and present unique challenges to system designers and operators. First, intermittent renewable energy resources power these systems, which break the notion of infinite, reliable, and controllable power supply. Second, these systems come in varying sizes, spanning over large geographical regions. The control of these dispersed and diverse systems raises scalability challenges. Third, the performance modeling and fault detection in sustainable energy systems is still an active research area. Finally, …

Accelerating Graphics Rendering On Risc-V Gpus, Joshua Simpson

Master's Theses

Graphics Processing Units (GPUs) are commonly used to accelerate massively parallel workloads across a wide range of applications from machine learning to cryptocurrency mining. The original application for GPUs, however, was to accelerate graphics rendering which remains popular today through video gaming and video rendering. While GPUs began as fixed function hardware with minimal programmability, modern GPUs have adopted a design with many programmable cores and supporting fixed function hardware for rasterization, texture sampling, and render output tasks. This balance enables GPUs to be used for general purpose computing and still remain adept at graphics rendering. Previous work at the …

Cloudbots: Autonomous Atmospheric Explorers, Akash Binoj

Honors Scholar Theses

The CloudBot is an autonomous weather balloon that operates on the principle of variable buoyancy to ascend and descend in the atmosphere. This project aims to develop a device that will collect atmospheric measurements and communicate them mid-flight. The apparatus consists of a helium-filled balloon, the robotic payload, and an air cell. The fixed-volume helium balloon at the top provides an upwards buoyancy force, while the air cell at the bottom can hold a variable amount of pressure to adjust the weight of the CloudBot. By doing so, it is able to travel in storm conditions and collect valuable atmospheric …

Structural Checking Tool Restructure And Matching Improvements, Derek Taylor

Graduate Theses and Dissertations

With the rising complexity and size of hardware designs, saving development time and cost by employing third-party intellectual property (IP) into various first-party designs has become a necessity. However, using third-party IPs introduces the risk of adding malicious behavior to the design, including hardware Trojans. Different from software Trojan detection, the detection of hardware Trojans in an efficient and cost-effective manner is an ongoing area of study and has significant complexities depending on the development stage where Trojan detection is leveraged. Therefore, this thesis research proposes improvements to various components of the soft IP analysis methodology utilized by the Structural …

Side-Channel Analysis On Post-Quantum Cryptography Algorithms, Tristen Teague

Computer Science and Computer Engineering Undergraduate Honors Theses

The advancements of quantum computers brings us closer to the threat of our current asymmetric cryptography algorithms being broken by Shor's Algorithm. NIST proposed a standardization effort in creating a new class of asymmetric cryptography named Post-Quantum Cryptography (PQC). These new algorithms will be resistant against both classical computers and sufficiently powerful quantum computers. Although the new algorithms seem mathematically secure, they can possibly be broken by a class of attacks known as side-channels attacks (SCA). Side-channel attacks involve exploiting the hardware that the algorithm runs on to figure out secret values that could break the security of the system. …

Unconventional Computation Including Quantum Computation, Bruce J. Maclennan

Faculty Publications and Other Works -- EECS

Unconventional computation (or non-standard computation) refers to the use of non-traditional technologies and computing paradigms. As we approach the limits of Moore’s Law, progress in computation will depend on going beyond binary electronics and on exploring new paradigms and technologies for information processing and control. This book surveys some topics relevant to unconventional computation, including the definition of unconventional computations, the physics of computation, quantum computation, DNA and molecular computation, and analog computation. This book is the content of a course taught at UTK.

Toward Reliable And Efficient Message Passing Software For Hpc Systems: Fault Tolerance And Vector Extension, Dong Zhong

Doctoral Dissertations

As the scale of High-performance Computing (HPC) systems continues to grow, researchers are devoted themselves to achieve the best performance of running long computing jobs on these systems. My research focus on reliability and efficiency study for HPC software.

First, as systems become larger, mean-time-to-failure (MTTF) of these HPC systems is negatively impacted and tends to decrease. Handling system failures becomes a prime challenge. My research aims to present a general design and implementation of an efficient runtime-level failure detection and propagation strategy targeting large-scale, dynamic systems that is able to detect both node and process failures. Using multiple overlapping …

Inventory Locating With Quuppa: The Design And Development Of A Real-Time Process Monitoring Web Application Solution, Dylan C. Moreland, Trevor J. Howell, John W. Takiff, Patrick S. Dillon, Theo E. Fritz, William K. Mcintyre

Industrial and Manufacturing Engineering

Viasat, Inc. requires precise inventory tracking at their production facility in San Diego, CA. Viasat has installed the Quuppa indoor real-time locating system (RTLS), which it uses to track the real-time position of high-value work-in-process items. In its current state, the system only displays in-the-moment location information, with no available functionality for storing historical data for review, analysis, or visualization. In addition, the data displayed is noisy and prone to significant random error. This paper provides an overview of RTLS methods and technologies, assesses alternative solutions to Viasat’s issue, demonstrates our RTLS integrated web app solution, analyzes its impact, and …

A Method For Monitoring Operating Equipment Effectiveness With The Internet Of Things And Big Data, Carl D. Hays Iii

Master's Theses

The purpose of this paper was to use the Overall Equipment Effectiveness productivity formula in plant manufacturing and convert it to measuring productivity for forklifts. Productivity for a forklift was defined as being available and picking up and moving containers at port locations in Seattle and Alaska. This research uses performance measures in plant manufacturing and applies them to mobile equipment in order to establish the most effective means of analyzing reliability and productivity. Using the Internet of Things to collect data on fifteen forklift trucks in three different locations, this data was then analyzed over a six-month period to …

A Secure Architecture For Defense Against Return Address Corruption, Grayson J. Bruner

Masters Theses

The advent of the Internet of Things has brought about a staggering level of inter-connectivity between common devices used every day. Unfortunately, security is not a high priority for developers designing these IoT devices. Often times the trade-off of security comes at too high of a cost in other areas, such as performance or power consumption. This is especially prevalent in resource-constrained devices, which make up a large number of IoT devices. However, a lack of security could lead to a cascade of security breaches rippling through connected devices. One of the most common attacks used by hackers is return …

Non-Volatile Memory Adaptation In Asynchronous Microcontroller For Low Leakage Power And Fast Turn-On Time, Jean Pierre Thierry Habimana

Graduate Theses and Dissertations

This dissertation presents an MSP430 microcontroller implementation using Multi-Threshold NULL Convention Logic (MTNCL) methodology combined with an asynchronous non-volatile magnetic random-access-memory (RAM) to achieve low leakage power and fast turn-on. This asynchronous non-volatile RAM is designed with a Spin-Transfer Torque (STT) memory device model and CMOS transistors in a 65 nm technology. A self-timed Quasi-Delay-Insensitive 1 KB STT RAM is designed with an MTNCL interface and handshaking protocol. A replica methodology is implemented to handle write operation completion detection for long state-switching delays of the STT memory device. The MTNCL MSP430 core is integrated with the STT RAM to create …

Cognitive Digital Twins For Smart Manufacturing, Muhammad Intizar Ali, Pankesh Patel, John G. Breslin, Ramy Harik, Amit Sheth

Publications

Smart manufacturing or Industry 4.0, a trend initiated a decade ago, aims to revolutionize traditional manufacturing using technology-driven approaches. Modern digital technologies such as the Industrial Internet of Things (IIoT), Big Data Analytics, Augmented/Virtual Reality, and Artificial Intelligence (AI) are the key enablers of new smart manufacturing approaches. The digital twin is an emerging concept whereby a digital replica can be built of any physical object. Digital twins are becoming mainstream; many organizations have started to rely on digital twins to monitor, analyze, and simulate physical assets and processes. The current use of digital twins for smart manufacturing is largely …