Computer and Systems Architecture Commons^™

System For Synchronizing Execution By A Processing Element Of Threads Within A Process Using A State Indicator Us:5553305, Robert Iannucci, Steven Gregor

Robert A Iannucci

No abstract provided.

Customizable Operating Systems, Jonathan Walpole, Crispin Cowan, Andrew P. Black, Jon Inouye, Calton Pu, Shanwei Cen

Computer Science Faculty Publications and Presentations

A customizable operating system is one that can adapt to improve its functionality or performance. The need for customizable and application-specific operating systems has been recognized for many years, but they have yet to appear in the commercial market. This paper explores the notion of operating system customizability and examines the limits of existing approaches. The paper begins by surveying system structuring approaches for the safe and efficient execution of customizable operating systems. Then it discusses the burden that existing approaches impose on application software, and explores techniques for reducing this burden. Finally, support for customizability in the Synthetix project …

Device And Physical Data Independence For Multimedia Presentations, Richard Staehli, Jonathan Walpole, David Maier

Computer Science Faculty Publications and Presentations

Multimedia computing promises access to any type of visual or aural medium on the desktop. But in this networked future, will every type of media be accessible from every terminal device? Current multimedia standards do not allow content that is authored for high-bandwidth workstations to scale down for low-bandwidth applications. The problem is that application requests are commonly interpreted as requests for the highest possible quality and resource overloads are handled by ad hoc methods. We can begin to solve this problem by specifying Quality of Service (QOS) requirements based on functionality rather than on content encoding and device capabilities.

Book Review: Reasoning Agents In A Dynamic World: The Frame Problem. Kenneth M. Ford And Patrick J. Hayes, Eds.,, Jozsef A. Toth

Jozsef A Toth Ph.D.

No abstract provided.

Scheduling Of Parallel Jobs On Dynamic, Heterogenous Networks, Dan Clark, Jeremy Casas, Steve Otto, Robert Prouty, Jonathan Walpole

Computer Science Faculty Publications and Presentations

In using a shared network of workstations for parallel processing, it is not only important to consider heterogeneity and differences in processing power between the workstations but also the dynamics of the system as a whole. In such a computing environment where the use of resources vary as other applications consume and release resources, intelligent scheduling of the parallel jobs onto the available resources is essential to maximize resource utilization. Despite this realization, however, there are few systems available that provide an infrastructure for the easy development and testing of these intelligent schedulers. In this paper, an infrastructure is presented …

A User-Level Process Package For Concurrent Computing, Ravi Konuru, Steve Otto, Jonathan Walpole, Robert Prouty, Jeremy Casas

Computer Science Faculty Publications and Presentations

A lightweight user-level process(ULP) package for parallel computing is described. Each ULP has its own register context, stack, data and heap space and communication with other ULPs is performed using locally synchronous, location transparent, message passing primitives. The aim of the package is to provide support for lightweight over-decomposition, optimized local communication and transparent dynamic migration. The package supports a subset of the Parallel Virtual Machine(PVM) interface[Sun90).

Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith

Robert A Iannucci

No abstract provided.

Script-Based Qos Specifications For Multimedia Presentations, Richard Staehli, Jonathan Walpole

Computer Science Faculty Publications and Presentations

Multimedia presentations can convey information not only by the sequence of events but by their timing. The correctness of such presentations thus depends on the timing of events as well as their sequence and content. This paper introduces a formal specification language for playback of real-time presentations. The main contribution of this language is a quality of service (QOS) specification that relaxes resolution and synchronization requirements for playback. Our definitions give a precise meaning to the correctness of a presentation. This specification language will form the basis for a QOS interface for reservation of operating system resources.

A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh

Computer Science: Faculty Publications and Other Works

This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.

A Study Of Dynamic Optimization Techniques: Lessons And Directions In Kernel Design, Calton Pu, Jonathan Walpole

Computer Science Faculty Publications and Presentations

The Synthesis kernel [21,22,23,27,28] showed that dynamic code generation, software feedback, and fine-grain modular kernel organization are useful implementation techniques for improving the performance of operating system kernels. In addition, and perhaps more importantly, we discovered that there are strong interactions between the techniques. Hence, a careful and systematic combination of the techniques can be very powerful even though each one by itself may have serious limitations. By identifying these interactions we illustrate the problems of applying each technique in isolation to existing kernels. We also highlight the important common under-pinnings of the Synthesis experience and present our ideas on …

Porting Chorus To The Pa-Risc: Building, Debugging, Testing And Validation, Ravi Konuru, Marion Hakanson, Jon Inouye, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation. This document describes the environment for building the Chorus kernel, the various kernel tests, and the debugging environment used for porting the Chorus operating system to the HP PA-RISC.

The information contained in this paper will be of interest to people who wish to:

• Use the PA-Chorus kernel for development and/or modification, • Know about the build environment for Chorus kernel on PA-RISC, • Know about the PA-Chorus approach to debugging, • …

Porting Chorus To The Pa-Risc: Overall Evaluation, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System kernel to the Hewlett-Packard 9000 Series 800 workstation. This document summarizes the matches and mis-matches between Chorus and the PA-RISC and outlines the general lessons learned during the project.

This document is intended for people who are interested in (a) the separation of machinedependent micro-kernel code from machine-independent micro-kernel code, (b) the interaction between operating system design and the PA-RISC architecture, and (c) the portability ofthe Chorus operating system.

The first report in the series, Porting Chorus to the PA-RISe: …

Porting Chorus To The Pa-Risc: Project Overview, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation. This document presents an overview of the project, and outlines the other reports in the series and the relationships between them.

Porting Chorus To The Pa-Risc: Booting, Jon Inouye, Ravi Konuru, Jonathan Walpole, Marion Hakanson

Computer Science Faculty Publications and Presentations

We started out with the low level Tut (HP-CX 2.0) boot code. One of our goals was to reuse as much of this code as possible, which would reduce the amount of low level code we would have to debug. This was very important, especially fiince the RP 9000/834 has a very complex I/O architecture and we lacked any sophisticated debugging tools. Writing the PA-Chorus boot code involved modifying the Tut code to match the Chorus startup sequence. In the remainder of this section, we present an overview of the PA-RISC boot mechanisms and the Chorus startup sequence. Sectlon 2 …

Porting Chorus To The Pa-Risc: Virtual Memory Manager, Jon Inouye, Marion Hakanson, Ravi Konuru, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document describes the port ofthe Chorus virtual memory manager to the Hewlett-Packard Precision Architecture rusc (PA-RISC) workstation. The information contained in this paper will be of interest to people who:

• intend to port the Chorus virtual memory section. • intend to port a virtual memory design to the Hewlett-Packard PA-RISC.

The reader is strongly encouraged to read the following PA-Chorus documents before reading this document:

• Technical Report CSE-92-3, Porting Chorus to the PA-RISC: Project Overview

Porting The Chorus Supervisor And Related Low-Level Functions To The Pa-Risc, Ravi Konuru, Marion Hakanson, Jon Inouye, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation.

The Supervisor is the name given by Chorus to a collection of low-level functions that are machine dependent and have to be implemented when Chorus is ported from one machine to another. The Supervisor is responsible for interrupt, trap and exception handling, managing low-level thread initialization, context switch, kernel initialization, managing simple devices (timer and console) and offering a low-level debugger. This document describes the port of the Supervisor and related low-level functions. …

High Performance Memory System Pct:Ep0199134, Robert Iannucci

Robert A Iannucci

No abstract provided.

The Fat-Pyramid: A Robust Network For Parallel Computation, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

This paper shows that a fat-pyramid of area Theta(A) built from processors of size lg A requires only O(lg^2 A) slowdown in bit-times to simulate any network of area A under very general conditions. Specifically, there is no restriction on processor size (amount of attached memory) or number of processors in the competing network, nor is the assumption of unit wire delay required. This paper also derives upper bounds on the slowdown required by a fat-pyramid to simulate a network of larger area in the case of unit wire delay.

Pipelining Data Compression Algorithms, R. L. Bailey, R. Mukkamala

Computer Science Faculty Publications

Many different data compression techniques currently exist. Each has its own advantages and disadvantages. Combining (pipelining) multiple data compression techniques could achieve better compression rates than is possible with either technique individually. This paper proposes a pipelining technique and investigates the characteristics of two example pipelining algorithms. Their performance is compared with other well-known compression techniques.

Parallel Machines: Parallel Machine Languages, Robert Iannucci

Robert A Iannucci

No abstract provided.

Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber

Robert A Iannucci

No abstract provided.

High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci

Robert A Iannucci

No abstract provided.

Randomized Routing On Fat-Trees, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …

Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber

Robert A Iannucci

No abstract provided.

Moment-Curvature-Thrust Relationships In Hybrid Members, Douglas Wrenn Fiala

Dissertations and Theses

In order to overcome the difficulties encountered in closed form solutions, moment-curvature-thrust relationships are developed for hybrid and nonhybrid cross sections utilizing an open form method. The use of horizontal sectors permits the inclusion of residual stresses and/or nonbilinear stress-strain relationships, if desired. Theoretical and experimental data are compared. Applications to circular tubes and other cross sections are discussed. Results indicate that open form solutions are feasible for calculating moment-curvature-thrust data. Hybrid cross sections are easily treated by open form solutions.