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Articles 121 - 125 of 125
Full-Text Articles in Theory and Algorithms
Scheduling Processors For Distributed, Critical, Real-Time Systems, Hari K. Narasimhamurthy
Scheduling Processors For Distributed, Critical, Real-Time Systems, Hari K. Narasimhamurthy
Electrical & Computer Engineering Theses & Dissertations
The development of a procedure to obtain cyclo-static schedules for distributed, critical real-time applications is presented in this thesis. The applications considered in this thesis are characterized by hard deadlines and periodic inputs. The applica tions are described by a data flow graph model which guarantees performance. Given the data flow graph representation, processors are scheduled to complete tasks as specified in the representation. The scheduling technique separates the scheduling of tasks in time and the assignment of processors to tasks. While different criteria exist for task scheduling, a schedule which minimizes latency and maximizes throughput is used in this …
Dynamic Task Scheduling For The Atamm Multicomputer Operating System Using Embedded Firmware On Microcontrollers, Sudhir Sastry
Dynamic Task Scheduling For The Atamm Multicomputer Operating System Using Embedded Firmware On Microcontrollers, Sudhir Sastry
Electrical & Computer Engineering Theses & Dissertations
A dynamic task scheduling strategy for the distributed processing of large grain dataflow algorithms using embedded firmware on an ATAMM testbed consisting of interconnected microcontrollers is presented in this thesis. The ODU/NASA developed Algorithm to Architecture Mapping Model, ATAMM, uses marked graph models to specify data and control flow for the execution of iterative, deterministic large grain dataflow algorithms in a multicomputing environment. The testbed consists of a bank of four 68HC11 microcontrollers that communicate over a token bus. The token bus arbitration scheme used is contention free and well suited for real-time computing applications. The execution of data flow …
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson's fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these "universal" networks …
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …