Programming Languages and Compilers Commons^™

Ultrasonic Sensor-Based Sound Synthesis Using Raspberry Pi Pico W, Niraj Jaishwal

Williams Honors College, Honors Research Projects

At the intersection of Human Computer Interaction and digital art, this project transforms simple motion into musical expression. It explores an interactive real-time sound synthesis system using ultrasonic sensors to generate continuous audio. The objective is to design a system that maps physical distances into musical parameters such as pitch and amplitude, which will create a responsive audio environment. Two ultrasonic sensors are used in combination with the Raspberry Pi Pico W microcontroller running CircuitPython and Adafruit Audio Hat for real-time sound output. One sensor controls the pitch of the generated tone, while the other controls volume. This enables expressive …

Side Channel Detection Of Pc Rootkits Using Nonlinear Phase Space, Rebecca Clark

Poster Presentations

Cyberattacks are increasing in size and scope yearly, and the most effective and common means of attack is through malicious software executed on target devices of interest. Malware threats vary widely in terms of behavior and impact and, thus, effective methods of detection are constantly being sought from the academic research community to offset both volume and complexity. Rootkits are malware that represent a highly feared threat because they can change operating system integrity and alter otherwise normally functioning software. Although normal methods of detection that are based on signatures of known malware code are the standard line of defense, …

Statically Controlled Synchronized Lane Architectures, Scott K. Pomerville

Dissertations, Master's Theses and Master's Reports

Modern superscalar processors dominate the field of computing. While dynamic execution allows for versatility in code, these processors are complex. Statically scheduled code has historically enabled simpler processor designs, but static scheduling cannot account for variables that are unknown at compile time. Furthermore, static scheduling has many inefficiencies, such as the need to insert a large number of nops for code in traditional Very Long Instruction Word (VLIW) processors. In this dissertation, we explore a novel architectural approach for statically scheduled code by breaking the code into several synchronous instruction streams. By representing code in a fundamentally new way, we …

Adaptive Neh With Constrained Nearest Neighbor Subtours For The Electric Vehicle Routing Problem With Time Windows, Andrew Struthers

All Master's Theses

The development of electric vehicles is currently considered one of the most innovative areas in manufacturing. Largely driven by the desire to reduce greenhouse emissions, electric vehicles are seen as a viable alternative to internal combustion engine cars. Starting from consumer cars, a dedicated effort is being made to translate this into commercial vehicles for freight and delivery. This research introduces a novel adaptive Nawaz, Enscore, Ham (NEH) algorithm with constrained nearest neighbor subtour (NEH-NN). This algorithm is tested on the standard benchmark problems in literature and used as a seed solution for the Genetic Algorithm (GA). The performance and …

Chatgpt As Metamorphosis Designer For The Future Of Artificial Intelligence (Ai): A Conceptual Investigation, Amarjit Kumar Singh (Library Assistant), Dr. Pankaj Mathur (Deputy Librarian)

Library Philosophy and Practice (e-journal)

Abstract

Purpose: The purpose of this research paper is to explore ChatGPT’s potential as an innovative designer tool for the future development of artificial intelligence. Specifically, this conceptual investigation aims to analyze ChatGPT’s capabilities as a tool for designing and developing near about human intelligent systems for futuristic used and developed in the field of Artificial Intelligence (AI). Also with the helps of this paper, researchers are analyzed the strengths and weaknesses of ChatGPT as a tool, and identify possible areas for improvement in its development and implementation. This investigation focused on the various features and functions of ChatGPT that …

Compilation Optimizations To Enhance Resilience Of Big Data Programs And Quantum Processors, Travis D. Lecompte

LSU Doctoral Dissertations

Modern computers can experience a variety of transient errors due to the surrounding environment, known as soft faults. Although the frequency of these faults is low enough to not be noticeable on personal computers, they become a considerable concern during large-scale distributed computations or systems in more vulnerable environments like satellites. These faults occur as a bit flip of some value in a register, operation, or memory during execution. They surface as either program crashes, hangs, or silent data corruption (SDC), each of which can waste time, money, and resources. Hardware methods, such as shielding or error correcting memory (ECM), …

Side-Channel Analysis On Post-Quantum Cryptography Algorithms, Tristen Teague

Computer Science and Computer Engineering Undergraduate Honors Theses

The advancements of quantum computers brings us closer to the threat of our current asymmetric cryptography algorithms being broken by Shor's Algorithm. NIST proposed a standardization effort in creating a new class of asymmetric cryptography named Post-Quantum Cryptography (PQC). These new algorithms will be resistant against both classical computers and sufficiently powerful quantum computers. Although the new algorithms seem mathematically secure, they can possibly be broken by a class of attacks known as side-channels attacks (SCA). Side-channel attacks involve exploiting the hardware that the algorithm runs on to figure out secret values that could break the security of the system. …

Mapping Renewal: How An Unexpected Interdisciplinary Collaboration Transformed A Digital Humanities Project, Elise Tanner, Geoffrey Joseph

Digital Initiatives Symposium

Funded by a National Endowment for Humanities (NEH) Humanities Collections and Reference Resources Foundations Grant, the UA Little Rock Center for Arkansas History and Culture’s “Mapping Renewal” pilot project focused on creating access to and providing spatial context to archival materials related to racial segregation and urban renewal in the city of Little Rock, Arkansas, from 1954-1989. An unplanned interdisciplinary collaboration with the UA Little Rock Arkansas Economic Development Institute (AEDI) has proven to be an invaluable partnership. One team member from each department will demonstrate the Mapping Renewal website and discuss how the collaborative process has changed and shaped …

Lecture 00: Opening Remarks: 46th Spring Lecture Series, Tulin Kaman

Mathematical Sciences Spring Lecture Series

Opening remarks for the 46th Annual Mathematical Sciences Spring Lecture Series at the University of Arkansas, Fayetteville.

Demand-Driven Execution Using Future Gated Single Assignment Form, Omkar Javeri

Dissertations, Master's Theses and Master's Reports

This dissertation discusses a novel, previously unexplored execution model called Demand-Driven Execution (DDE), which executes programs starting from the outputs of the program, progressing towards the inputs of the program. This approach is significantly different from prior demand-driven reduction machines as it can execute a program written in an imperative language using the demand-driven paradigm while extracting both instruction and data level parallelism. The execution model relies on an executable Single Assignment Form which serves both as the internal representation of the compiler as well as the Instruction Set Architecture (ISA) of the machine. This work develops the instruction set …

Developing 5gl Concepts From User Interactions, David Stuckless Meyer

Masters Theses

In the fulfilling of the contracts generated in Test Driven Development, a developer could be said to act as a constraint solver, similar to those used by a 5th Generation Language(5GL). This thesis presents the hypothesis that 5GL linguistic mechanics, such as facts, rules and goals, will be emergent in the communications of developer pairs performing Test Driven Development, validating that 5GL syntax is congruent with the ways that practitioners communicate. Along the way, nomenclatures and linguistic patterns may be observed that could inform the design of future 5GL languages.

A Compiler Target Model For Line Associative Registers, Paul S. Eberhart

Theses and Dissertations--Electrical and Computer Engineering

LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.

Feature-Based Transfer Learning In Natural Language Processing, Jianfei Yu

Dissertations and Theses Collection (Open Access)

In the past few decades, supervised machine learning approach is one of the most important methodologies in the Natural Language Processing (NLP) community. Although various kinds of supervised learning methods have been proposed to obtain the state-of-the-art performance across most NLP tasks, the bottleneck of them lies in the heavy reliance on the large amount of manually annotated data, which is not always available in our desired target domain/task. To alleviate the data sparsity issue in the target domain/task, an attractive solution is to find sufficient labeled data from a related source domain/task. However, for most NLP applications, due to …

Efficient Attribute-Based Encryption With Blackbox Traceability, Shengmin Xu, Guomin Yang, Yi Mu, Ximeng Liu

Research Collection School Of Computing and Information Systems

Traitor tracing scheme can be used to identify a decryption key is illegally used in public-key encryption. In CCS’13, Liu et al. proposed an attribute-based traitor tracing (ABTT) scheme with blackbox traceability which can trace decryption keys embedded in a decryption blackbox/device rather than tracing a well-formed decryption key. However, the existing ABTT schemes with blackbox traceability are based on composite order group and the size of the decryption key depends on the policies and the number of system users. In this paper, we revisit blackbox ABTT and introduce a new primitive called attribute-based set encryption (ABSE) based on key-policy …

Integrated Reward Scheme And Surge Pricing In A Ride Sourcing Market, Hai Yang, Chaoyi Shao, Hai Wang, Jieping Ye

Research Collection School Of Computing and Information Systems

Surge pricing is commonly used in on-demand ride-sourcing platforms (e.g., Uber, Lyft and Didi) to dynamically balance demand and supply. However, since the price for ride service cannot be unlimited, there is usually a reasonable or legitimate range of prices in practice. Such a constrained surge pricing strategy fails to balance demand and supply in certain cases, e.g., even adopting the maximum allowed price cannot reduce the demand to an affordable level during peak hours. In addition, the practice of surge pricing is controversial and has stimulated long debate regarding its pros and cons. In this paper, to address the …

Just In Time Assembly (Jita) - A Run Time Interpretation Approach For Achieving Productivity Of Creating Custom Accelerators In Fpgas, Sen Ma

Graduate Theses and Dissertations

The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs include: 1) knowledge of hardware programming models, 2) the need to work within the vendor specific CAD tools and hardware synthesis. This thesis presents a series of published papers that explore different aspects of a new approach being developed to remove the barriers and enable programmers to compile accelerators on next generation reconfigurable manycore architectures. The approach is entitled Just In Time Assembly (JITA) of hardware accelerators. The approach has been defined …

Front Matter: Proceedings Of The Maics 2016 Conference, University Of Dayton

Content presented at the MAICS conference

Front matter contains:

• A list of program chairs and committee members
• Foreword to the proceedings by James P. Buckley, conference chair; Saverio Perugini, general chair

Editors: Phu H. Phung, University of Dayton; Ju Shen, University of Dayton; Michael Glass, Valparaiso University

Design, Programming, And User-Experience, Kaila G. Manca

Honors Scholar Theses

This thesis is a culmination of my individualized major in Human-Computer Interaction. As such, it showcases my knowledge of design, computer engineering, user-experience research, and puts into practice my background in psychology, com- munications, and neuroscience.

I provided full-service design and development for a web application to be used by the Digital Media and Design Department and their students.This process involved several iterations of user-experience research, testing, concepting, branding and strategy, ideation, and design. It lead to two products.

The first product is full-scale development and optimization of the web appli- cation.The web application adheres to best practices. It was …

Study Of Parallel Programming Models On Computer Clusters With Accelerators, Chenggang Lai

Graduate Theses and Dissertations

In order to reach exascale computing capability, accelerators have become a crucial part in developing supercomputers. This work examines the potential of two latest acceleration technologies, Intel Many Integrated Core (MIC) Architecture and Graphics Processing Units (GPUs). This thesis applies three benchmarks under 3 different configurations, MPI+CPU, MPI+GPU, and MPI+MIC. The benchmarks include intensely communicating application, loosely communicating application, and embarrassingly parallel application. This thesis also carries out a detailed study on the scalability and performance of MIC processors under two programming models, i.e., offload model and native model, on the Beacon computer cluster.

According to different benchmarks, the results …

Cuda Web Api Remote Execution Of Cuda Kernels Using Web Services, Massimo J. Becker

Master's Theses

Massively parallel programming is an increasingly growing field with the recent introduction of general purpose GPU computing. Modern graphics processors from NVIDIA and AMD have massively parallel architectures that can be used for such applications as 3D rendering, financial analysis, physics simulations, and biomedical analysis. These massively parallel systems are exposed to programmers through in- terfaces such as NVIDIAs CUDA, OpenCL, and Microsofts C++ AMP. These frame- works expose functionality using primarily either C or C++. In order to use these massively parallel frameworks, programs being implemented must be run on machines equipped with massively parallel hardware. These requirements limit …

Architecture For A Flexible And Scalable Simulation Engine, Robert C. Holcomb Jr.

Computational Modeling & Simulation Engineering Theses & Dissertations

Simulation is used by many different industries to gain insight on actions and decisions that may be too dangerous or costly to perform in reality. Although the use of computers to assist with modeling and simulation has been studied for quite a while, computer infrastructure, hardware, and capabilities are changing at a rapid pace. Computer software once written is difficult and costly to change, especially in order to take advantage of the advances in computer hardware. This thesis focuses on the design and implementation of a software simulation architecture that allows flexibility in the modeling conducted and scalability in the …

Max Flow Spill Code Placement Algorithm Implemented In Gcc 4.4.3, Stephen Robert Beard

Computer Engineering

The placement of spill code plays an important role in the register allocator of an optimizing compiler. Many computer architectures possess a register linkage convention that dictates which registers are preserved across function calls and which are not. This project addresses the problem of optimizing spill code that is associated with register linkage conventions.

This algorithm was created by Dr. Chris Lupo and is described in the paper Beyond Register Allocation: a Novel Algorithm for Spill-Code Placement. The algorithm was implemented for GCC 2.5.7 for a PA-RISC architecture [4]. The work in this project will involve porting the existing code …

Filling The Ontology Space For Coalition Battle Management Language, Charles Turnitsa, Curtis Blais, Andreas Tolk

Computational Modeling & Simulation Engineering Faculty Publications

The Coalition Battle Management Language is a language for representing and exchanging plans, orders, and reports across live, constructive and robotic forces in multi-service, multi-national and multi-organizational operations. Standardization efforts in the Simulation Interoperability Standards Organization seek to define this language through three parallel activities: (1) specify a sufficient data model to unambiguously define a set of orders using the Joint Command, Control, and Consultation Information Exchange Data Model (JC3IEDM) as a starting point; (2) develop a formal grammar (lexicon and production rules) to formalize the definition of orders, requests, and reports; (3) develop a formal battle management ontology to …

Directflow: A Domain-Specific Language For Information-Flow Systems, Andrew P. Black, Chuan-Kai Lin

Computer Science Faculty Publications and Presentations

Programs that process streams of information are commonly built by assembling reusable information-flow components. In some systems the components must be chosen from a pre-defined set of primitives; in others the programmer can create new custom components using a general-purpose programming language. Neither approach is ideal: restricting programmers to a set of primitive components limits the expressivity of the system, while allowing programmers to define new components in a general-purpose language makes it difficult or impossible to reason about the composite system. We advocate defining information-flow components in a domain-specific language (DSL) that enables us to infer the properties of …

Personal Information Management. A Framework For Development Of Personalisable Web Based Services, Christopher Fuchs

Theses

The thesis research proposed herein will model, analyse and implement strategies for the development of personalised services. The goal of the research work is to design and implement a framework which supports developers by minimising the effort required in implementing personalised services. This includes the ability to react to localisation changes and to present proper information. An overall design goal is the independency of most components from each other which will be attained through the use of standard technologies and protocols and the consistent use of a component model. The result will include the proposed framework and the analyses of …

Post Register Allocation Spill Code Optimization, Christopher Lupo, Kent Wilken

Computer Science and Software Engineering

A highly optimized register allocator should provide an efficient placement of save/restore code for procedures that contain calls. This paper presents a new approach to placing callee-saved save and restore instructions that generalizes Chow's shrink-wrapping technique (Chow 1988). An efficient, profile-guided, hierarchical spill code placement algorithm is used to analyze the structure of a procedure to calculate the minimum dynamic execution count locations to place callee-saved save and restore code. The algorithm is implemented in the Gnu Compiler Collection and has been tested on the SPEC CPU2000 Integer Benchmark suite. Results show that the technique reduces the number of dynamic …

Programmable Process Flow Networks, Filip D. Cuckov

Electrical & Computer Engineering Theses & Dissertations

A model that introduces programmability to processes occurring in a cargo terminal simulation through the use of a process language is presented in this thesis. The model provides a means for a straight-forward definition, and redefinition of changing processes, their incorporation in the simulation architecture and efficient execution. The model was built to investigate a solution for transforming the cargo terminal simulation CPortS into a process-oriented simulation without hard-coded processes. The approach taken separates the system into an architecture and a set of processes which utilize and interact with the architecture's resources and infrastructure. The processes that take place within …

Jsb Composability And Web Services Interoperability Via Extensible Modeling & Simulation Framework (Xmsf), Model Driven Architecture (Mda), Component Repositories, And Web-Based Visualization, Don Brutzman, Andreas Tolk

Computational Modeling & Simulation Engineering Faculty Publications

"Study Report prepared for the U. S. Air Force, Joint Synthetic Battlespace Analysis of Technical Approaches (ATA) Studies & Prototyping"

Overview: This paper summarizes research work conducted by organizations concerned with interoperable distributed information technology (IT) applications, in particular the Naval Postgraduate School (NPS) and Old Dominion University (ODU). Although the application focus is distributed modeling & simulation (M&S) the results and findings are in general easily applicable to other distributed concepts as well, in particular the support of operations by M&S applications, such as distributed mission operations. The core idea of this work is to show the necessity of …

An Intelligent Real-Time System Architecture Implemented In Ada, Michael A. Whelan

Theses and Dissertations

Conventional real-time systems are fully deterministic allowing for off-line, optimal, task scheduling under all circumstances. Real-time intelligent systems add non-deterministic task execution times and non- deterministic task sets for scheduling purposes. Non-deterministic task sets force intelligent real-time systems to trade-off execution time with solution quality during run-time and perform dynamic task scheduling. Four basic design considerations addressing those tradeoffs have been identified: control reasoning, focus of attention, parallelism, and algorithm efficacy. Non-real- time intelligent systems contain an environment sensor, a model of the environment, a reasoning process, and a large collection of procedural processes. Real-time intelligent systems add to these …

Simulator For Concurrent Processing Data Flow Architectures, Mahyar R. Malekpour

Electrical & Computer Engineering Theses & Dissertations

A software simulator capable of simulating execution of an algorithm graph on a given system under the Algorithm To Architecture Mapping Model (ATAMM) rules is presented in this thesis. ATAMM is capable of modeling the execution of large-grained algorithms on distributed data flow architectures. Investigating the behavior and determining the performance of an ATAMM based system requires the aid of software tools. The ATAMM Simulator presented in this thesis is capable of determining the behavior, performance, and reliability of a system without having to build a hardware prototype. Case studies are performed on four algorithms to demonstrate the capabilities of …