Computer Sciences Commons^™

Rudy Rucker's Spirograph, Rudy Rucker

SWITCH

This article showcases the main aspects of how this spirograph was to be used. The spirograph is part of Rudy Rucker’s quest for the gnarl. The main page shows how to download this spirograph and how to utilize the program to its full potential.

Scheduling Processors For Distributed, Critical, Real-Time Systems, Hari K. Narasimhamurthy

Electrical & Computer Engineering Theses & Dissertations

The development of a procedure to obtain cyclo-static schedules for distributed, critical real-time applications is presented in this thesis. The applications considered in this thesis are characterized by hard deadlines and periodic inputs. The applica­ tions are described by a data flow graph model which guarantees performance. Given the data flow graph representation, processors are scheduled to complete tasks as specified in the representation. The scheduling technique separates the scheduling of tasks in time and the assignment of processors to tasks. While different criteria exist for task scheduling, a schedule which minimizes latency and maximizes throughput is used in this …

Adaptive Integration Of Audio And Visual Information Using Discrete And Semi-Continuous Hidden Markov Models In Audiovisual Automatic Speech Recognition, Qin Su

Electrical & Computer Engineering Theses & Dissertations

An audiovisual semi-continuous hidden Markov model (HMM)-based Automatic Speech Recognition (ASR) system and an improved method of integrating audio and visual information in an audiovisual discrete HMM-based ASR system are investigated.

In the audiovisual discrete HMM, an adaptive integration formulation is employed, which incorporates the integration into the HMM at a pre-categorical stage. A visual weighting parameter is determined automatically, which allows the relative contribution of audio and visual information to be adjusted adaptively. Using an adaptive weight, the accuracy increased by 13% compared to the same model with no adaptive weight.

The semi-continuous HMM is a class of models …

Variable Step Size Lms Adaptive Filters With Delayed Coefficient Updating, Guixian Xu

Electrical & Computer Engineering Theses & Dissertations

A new approach to delayed LMS adaptive filtering is presented, which uses a variable step size for coefficient updating to increase convergence speed and improve tracking characteristics. The new algorithm, called delayed variable step size LMS (DVLMS), is explained, analyzed, and simulated to experimentally determine performance characteristics. Three different strategies for adjusting the step size are examined, and their performance is compared. Also, simulation results are presented to show that the proposed DVLMS systems provide faster convergence and lower mis-adjustment than previously proposed DLMS systems.

Low-Degree Spanning Trees Of Small Weight, Samir Khuller, Balaji Raghavachari, Neal Young

Dartmouth Scholarship

Given n points in the plane, the degree-K spanning-tree problem asks for a spanning tree of minimum weight in which the degree of each vertex is at most K. This paper addresses the problem of computing low-weight degree-K spanning trees for $K > 2$. It is shown that for an arbitrary collection of n points in the plane, there exists a spanning tree of degree 3 whose weight is at most 1.5 times the weight of a minimum spanning tree. It is shown that there exists a spanning tree of degree 4 whose weight is at most 1.25 times …

Simulator For The Performance Analysis Of Cpm Schemes In An Indoor Wireless Environment, Ronald Chua

Theses : Honours

A software simulator for characterising Continuous Phase Modulation (CPM) schemes in an indoor multipath environment has been developed using SIMULINK and MATLAB. The simulator is capable of simulating a wide range of CPM schemes to determine bandwidth efficiency and robustness to additive white Gaussian noise (AWGN) and Rician fading. Initial trials of the simulator indicate that the simulator is functioning correctly. Eventually, the simulator will be used to determine the most suitable modulation scheme for the development of an actual indoor wireless system.

Packet Routing In Networks With Long Wires, Ronald I. Greenberg, Hyeong-Cheol Oh

Computer Science: Faculty Publications and Other Works

In this paper, we examine the packet routing problem for networks with wires of differing length. We consider this problem in a network independent context, in which routing time is expressed in terms of "congestion" and "dilation" measures for a set of packet paths. We give, for any constant ϵ > 0, a randomized on-line algorithm for routing any set of Npackets in O((C lg^ϵ(Nd) + D lg(Nd))/lg lg(Nd)) time, where C is the maximum congestion and D is the length of the longest path, both taking wire delays into …

Text Independent Speaker Verification Using Binary-Pair Partitioned Neural Networks, Claude A. Norton Iii

Electrical & Computer Engineering Theses & Dissertations

A method is presented for the application of binary-pair partitioned neural networks to the task of speaker verification. This technique is based on a previously developed neural network classifier for speaker identification.

The main focus of this research was the development and testing of the algorithms necessary to extend the binary-pair partitioning approach from speaker identification to speaker verification. The method is based on the development of a user profile which is obtained from discriminative data provided by the binary-pair partitioned neural networks.

Experimental results are provided which demonstrate the viability of this approach, using the TIMIT speech corpus for …

Fault Tolerance In Critical Real-Time Systems, Balaji Tirukarneswaran

Electrical & Computer Engineering Theses & Dissertations

Critical real-time applications require work to be completed before a predefined deadline, else the consequences may be catastrophic. The anticipation of faults in such systems necessitates the need for fault tolerance. Fault tolerance can be achieved in many different ways. A real-time system designer may impose restrictions on any of the system performance measures such as the latency, throughput and number of processors, depending on the type of application. In this work, several different fault tolerant strategies for any given DFG (Data Flow Graph) are discussed. DFG models are developed using the strategies and the resulting worst case performances a.re …

Real-Time Communication In The Algorithm To Architecture Mapping Model, Somesh M. Varma

Electrical & Computer Engineering Theses & Dissertations

The objective of this thesis is to analyze schedules of communication resources to obtain deterministic and contention-free communication in the Algorithm To Architecture Mapping Model (ATAMM). In ATAMM, performance must be deterministic to guarantee meeting deadlines. It is difficult to achieve deterministic performance in the presence of contention during communication. This thesis develops new data-flow models to study and analyze different schedules of communication resources to achieve deterministic and contention-free communication. These models are the Synchronous Communication Marked Graph (SCMG) and the Asynchronous Communication Marked Graph (ACMG). The SCMG is based on message passing synchronous communication. It defines schedules for …

Open-Loop State-Space Model Identification From Closed-Loop Data, Lori Guy

Mechanical & Aerospace Engineering Theses & Dissertations

This thesis provides an investigation of a system identification algorithm which identifies an open-loop state-space model from a linear system that is operating under closed-loop conditions. In order to investigate the system identification algorithm some basic ideas of system identification theory are reviewed. Examples using simulated data are presented to characterize the effects of varying the parameters for open-loop and closed-loop system identification processes. Both noise· free and noise contaminated cases are simulated. Linear Quadratic Gaussian (LQG) control theory is reviewed and the motivation for using iterative LQG control feedback is discussed. The derivation of the proposed system identification algorithm …

Approximation Algorithms: Good Solutions To Hard Problems, Ran Libeskind-Hadas

All HMC Faculty Publications and Research

Consider a computer network represented by an undirected graph where the vertices represent computer nodes and the edges represent links between the nodes. Since some of the links in the network may become faulty, link testing devices are placed at some of the nodes. A tester at a particular node can test all links incident to that node. Since the testers are expensive, however, we wish to deploy the minimum number of these devices such that every link is incidient to at least one node containing a tester. In graph theoretic terms, a vertex cover is a subset of the …

Finding Connected Components On A Scan Line Array Processor, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

This paper provides a new approach to labeling the connected components of an n x n image on a scan line array processor (comprised of n processing elements). Variations of this approach yield an algorithm guaranteed to complete in o(n lg n) time as well as algorithms likely to approach O(n) time for all or most images. The best previous solutions require using a more complicated architecture or require Omega(n lg n) time. We also show that on a restricted version of the architecture, any algorithm requires Omega(n lg n) time in the worst case.

Rule Extraction: From Neural Architecture To Symbolic Representation, Gail A. Carpenter, Ah-Hwee Tan

Research Collection School Of Computing and Information Systems

This paper shows how knowledge, in the form of fuzzy rules, can be derived from a supervised learning neural network called fuzzy ARTMAP. Rule extraction proceeds in two stages: pruning, which simplifies the network structure by removing excessive recognition categories and weights; and quantization of continuous learned weights, which allows the final system state to be translated into a usable set of descriptive rules. Three benchmark studies illustrate the rule extraction methods: (1) Pima Indian diabetes diagnosis, (2) mushroom classification and (3) DNA promoter recognition. Fuzzy ARTMAP and ART-EMAP are compared with the ADAP algorithm, the k nearest neighbor system, …

A Linear-Time Recognition Algorithm For P4-Reducible Graphs, B. Jamison, S. Olariu

Computer Science Faculty Publications

The P₄-reducible graphs are a natural generalization of the well-known class of cographs, with applications to scheduling, computational semantics, and clustering. More precisely, the P₄-reducible graphs are exactly the graphs none of whose vertices belong to more than one chordless path with three edges. A remarkable property of P₄-reducible graphs is their unique tree representation up to isomorphism. In this paper we present a linear-time algorithm to recognize P₄-reducible graphs and to construct their corresponding tree representation.

An Analysis Of Bayesian Networks As Classifiers, Gregory C. Ahlquist

Theses and Dissertations

An analysis of Bayesian networks as classifiers is presented. This analysis results in an algorithm and several tools related to Bayesian network classifiers. The tools calculate and display the decision regions for two level Bayesian network classifiers. They collectively provide an approach to analyze the effects of changing network parameters on the network's decision regions. The algorithm defines a Bayesian network classifier to solve traditional classification problems. The algorithm is data driven, meaning that the resulting Bayesian network classifier is uniquely tuned to the classification problem at hand. Also, the algorithm contains procedures for defining the topology of a Bayesian …

The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

This paper shows that a fat-pyramid of area Θ(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more …

Logging Subsystem Performance: Model And Evaluation, Thomas K. Clark

Dissertations and Theses

Transaction logging is an integral part of ensuring proper transformation of data from one state to another in modern data management. Because of this, the throughput of the logging subsystem can be critical to the throughput of an application. The purpose of this research is to break the log bottleneck at minimum cost.

We first present a model for evaluating a logging subsystem, where a logging subsystem is made up of a log device, a log backup device, and the interconnect algorithm between the two, which we term the log backup method. Included in the logging model is a set …

Improved Algorithms For Bipartite Network Flow, Ravindra K. Ahuja, James B. B. Orlin, Clifford Stein, Robert E. Tarjan

Dartmouth Scholarship

In this paper, network flow algorithms for bipartite networks are studied. A network G = (V,E) is called bipartite if its vertex set V can be partitioned into two subsets V_1 and V_2 such that all edges have one endpoint in V_1 and the other in $V_2 $. Let $n = |V|, n_1 = |V_1 | , n_2 = |V_2 |, m = |E| and assume without loss of generality that n_1 \leqslant n_2. A bipartite network is called unbalanced if n_1 \ll n_2 $ and balanced otherwise. (This notion is necessarily imprecise.) It is shown that several maximum flow …

Defining Locally Shared Memory Constructs For Special Purpose Parallel Architectures, David J. Nielsen

Electrical & Computer Engineering Theses & Dissertations

Locally shared memory systems offer significant advantages over other parallel processing systems for specific classes of problems. Locally shared memory systems tend to be easier to program because explicit passing of messages is not necessary. The goal in defining a locally shared memory system is to allow only a small number of processors access to any single memory. If this goal is met, locally shared memory systems provide an architecture which is relatively simple to implement.

To make shared memory architectures attractive to designers of special purpose parallel architectures, the architectures must be scalable. To be scalable, the number of …

Genetic Algorithms And Artificial Life, Melanie Mitchell, Stephanie Forrest

Computer Science Faculty Publications and Presentations

Genetic algorithms are computational models of evolution that play a central role in many artificial-life models. We review the history and current scope of research on genetic algorithms in artificial life, giving illustrative examples in which the genetic algorithm is used to study how learning and evolution interact, and to model ecosystems, immune system, cognitive systems, and social systems. We also outline a number of open questions and future directions for genetic algorithms in artificial-life research

Polylog Depth Circuits For Integer Factoring And Discrete Logarithms, Jonathan P. Sorenson

Scholarship and Professional Work - LAS

AbstractIn this paper, we develop parallel algorithms for integer factoring and for computing discrete logarithms. In particular, we give polylog depth probabilistic boolean circuits of subexponential size for both of these problems, thereby solving an open problem of Adleman and Kompella.

Existing sequential algorithms for integer factoring and discrete logarithms use a prime base which is the set of all primes up to a bound B. We use a much smaller value for B for our parallel algorithms than is typical for sequential algorithms. In particular, for inputs of length n, by setting B = nlogdn with d a positive …

Dynamic Task Scheduling For The Atamm Multicomputer Operating System Using Embedded Firmware On Microcontrollers, Sudhir Sastry

Electrical & Computer Engineering Theses & Dissertations

A dynamic task scheduling strategy for the distributed processing of large grain dataflow algorithms using embedded firmware on an ATAMM testbed consisting of interconnected microcontrollers is presented in this thesis. The ODU/NASA developed Algorithm to Architecture Mapping Model, ATAMM, uses marked graph models to specify data and control flow for the execution of iterative, deterministic large grain dataflow algorithms in a multicomputing environment. The testbed consists of a bank of four 68HC11 microcontrollers that communicate over a token bus. The token bus arbitration scheme used is contention free and well suited for real-time computing applications. The execution of data flow …

Adaptive Execution Of Data Parallel Computations On Networks Of Heterogeneous Workstations, Robert Prouty, Steve Otto, Jonathan Walpole

Computer Science Faculty Publications and Presentations

Parallel environments consisting of a network of heterogeneous workstations introduce an inherently dynamic environment that differs from multicomputers. Workstations are usually considered “shared” resources while multicomputers provide dedicated processing power. The number of workstations available for use is continually changing; the parallel machine presented by the network is in effect continually reconfiguring itself. Application programs must effectively adapt to the changing number of processing nodes while maintaining computational efficiency. This paper examines methods for adapting to this dynamic environment within the framework of explicit message passing under the data parallel programming model. We present four requirements which we feel a …

Effective Parallel Algorithm Animation, Paul W. Chase

Theses and Dissertations

The AFIT Algorithm Animation Research Facility AAARF was developed by the Air Force Institute of Technology AFIT as a teaching aid for data structures and algorithm design. In particular, an extensive set of performance animations has been developed for the Intel iPSC Hypercube parallel processing system. This research focuses in part on developing animation support for discrete event simulation, mission routing, and evolutionary algorithms based on abstract representations of parallel algorithm behavior. The effort also builds extensions to the AAARF system and examines direction for further research. An innovative adaptable application-specific animation construction environment has been designed and implemented. The …

A Topology-Aware Collision Resolution Algorithm, Lewis Barnett Iii

Department of Math & Statistics Technical Report Series

A new collision resolution algorithm called the Space Division Multiple Access protocol (SDMA) is presented. SDMA gains a performance advantage over similar protocols by using information about the positions of stations on the network. The protocol can operate asynchrononsly on a broadcast bus, allowing variable sized packet traffic. Through simulation the protocol is demonstrated to have better performance than Ethernet and the Capetanakis Tree protocol, a similar collision resolution protocol, under some traffic conditions. In particular, under heavy loads, SDMA displays better average throughput and lower variance of delay than Ethernet. The protocol demonstrates a performance bias based on the …

A Greedy Hypercube-Labeling Algorithm, D. Bhagavathi, C. E. Grosch, S. Olariu

Computer Science Faculty Publications

Due to its attractive topological properties, the hypercube multiprocessor has emerged as one of the architectures of choice when it comes to implementing a large number of computational problems. In many such applications, Gray-code labelings of the hypercube are a crucial prerequisite for obtaining efficient algorithms. We propose a greedy algorithm that, given an n-dimensional hypercube H with N=2² nodes, returns a Gray-code labeling of H, that is, a labeling of the nodes with binary strings of length n such that two nodes are neighbors in the hypercube if, and only if, their labels differ in exactly …

Universal Wormhole Routing, Ronald I. Greenberg, Hyeong-Cheol Oh

Computer Science: Faculty Publications and Other Works

We examine the wormhole routing problem in terms of the "congestion" c and "dilation" d for a set of packet paths. We show, with mild restrictions, that there is a simple randomized algorithm for routing any set of P packets in O(cdη + cLηlog P) time, where L is the number of flits in a packet, and η = min {d,L]; only a constant number of flits are stored in each queue at any time. Using this result, we show that a fat-tree network of area Θ(A) can simulate wormhole routing on any network of comparable area with O(log 3 …

Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih

Computer Science: Faculty Publications and Other Works

We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that have linear-time sequential solutions rather than limiting attention to the ``river-routing'' context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN/lglgN) time on a CRCW PRAM, both with optimal work (processor-time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor bounds as long as only one side of …

Cyclo-Static Scheduling Of Large Grain Dataflow Algorithms On A Local Area Atamm Multicomputing Testbed, Sudeepto Roy

Electrical & Computer Engineering Theses & Dissertations

A strategy for cyclo-statically scheduling deterministic large grain dataflow (LGDF) algorithms for distributed execution on loosely coupled multicomputer architectures is presented in this research. The computational paradigm used is the ODU/NASA developed Algorithm To Architecture Mapping Model (ATAMM), which consists of marked graphs and Gantt chart representations that model the iterative execution of deterministic LGDF algorithms for different values of throughput and computation time. It is postulated that the behavior of these algorithms could be represented by the aggregate execution of an ensemble of cyclically shifted threads of a specific node sequence. Assuming the existence of one or more such …