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Articles 1 - 21 of 21
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow
Model Development And Assessment Of The Gate Network In A High-Performance Sic Power Module, William Austin Curbow
Graduate Theses and Dissertations
The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to offer remedies to these issues to increase the overall performance, robustness, and reliability of the technology. In order to accomplish this goal, a highly accurate model of the gate network is developed through three methods of parameter extraction: calculation, simulation, and measurement. A SPICE model of the gate network is developed to analyze four electrical issues in a high-speed, SiC-based power module including the necessary internal gate resistance for damping under-voltage and over-voltage transients, the disparity …
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Ronald Greenberg
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Ronald Greenberg
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
Ronald Greenberg
This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a …
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Ronald Greenberg
This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson's fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these "universal" networks …
At The Tone, The Time Will Be... Unknown – A Perspective On The Evolution Of Time In Telecommunications, Robert Iannucci
At The Tone, The Time Will Be... Unknown – A Perspective On The Evolution Of Time In Telecommunications, Robert Iannucci
Robert A Iannucci
No abstract provided.
Embedded Systems As Datacenters, Robert Iannucci
Embedded Systems As Datacenters, Robert Iannucci
Robert A Iannucci
No abstract provided.
Platform Thinking In Embedded Systems, Robert Iannucci
Platform Thinking In Embedded Systems, Robert Iannucci
Robert A Iannucci
No abstract provided.
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
Computer Science: Faculty Publications and Other Works
This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a …
Configuring Client Software Using Remote Notification Us:6219698, Robert Iannucci, Chris Weikart
Configuring Client Software Using Remote Notification Us:6219698, Robert Iannucci, Chris Weikart
Robert A Iannucci
No abstract provided.
Computer System For Simulating Physical Processes Using Multiple Integer State Vectors Us:5594671, Hudong Chen, Peter Churchill, Robert Iannucci, Kim Molvig, Gregory Papadopoulos, Stephen Remondi, Christopher Teixeira, Kenneth Traub
Computer System For Simulating Physical Processes Using Multiple Integer State Vectors Us:5594671, Hudong Chen, Peter Churchill, Robert Iannucci, Kim Molvig, Gregory Papadopoulos, Stephen Remondi, Christopher Teixeira, Kenneth Traub
Robert A Iannucci
No abstract provided.
System For Synchronizing Execution By A Processing Element Of Threads Within A Process Using A State Indicator Us:5553305, Robert Iannucci, Steven Gregor
System For Synchronizing Execution By A Processing Element Of Threads Within A Process Using A State Indicator Us:5553305, Robert Iannucci, Steven Gregor
Robert A Iannucci
No abstract provided.
Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith
Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith
Robert A Iannucci
No abstract provided.
High Performance Memory System Pct:Ep0199134, Robert Iannucci
High Performance Memory System Pct:Ep0199134, Robert Iannucci
Robert A Iannucci
No abstract provided.
Parallel Machines: Parallel Machine Languages, Robert Iannucci
Parallel Machines: Parallel Machine Languages, Robert Iannucci
Robert A Iannucci
No abstract provided.
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson's fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these "universal" networks …
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …
Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber
Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber
Robert A Iannucci
No abstract provided.
High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci
High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci
Robert A Iannucci
No abstract provided.
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …
Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber
Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber
Robert A Iannucci
No abstract provided.