VLSI and Circuits, Embedded and Hardware Systems Commons^™

Intrinsic Functions For Securing Cmos Computation: Variability, Modeling And Noise Sensitivity, Xiaolin Xu

Doctoral Dissertations

A basic premise behind modern secure computation is the demand for lightweight cryptographic primitives, like identifier or key generator. From a circuit perspective, the development of cryptographic modules has also been driven by the aggressive scalability of complementary metal-oxide-semiconductor (CMOS) technology. While advancing into nano-meter regime, one significant characteristic of today's CMOS design is the random nature of process variability, which limits the nominal circuit design. With the continuous scaling of CMOS technology, instead of mitigating the physical variability, leveraging such properties becomes a promising way. One of the famous products adhering to this double-edged sword philosophy is the Physically …

Variation Aware Placement For Efficient Key Generation Using Physically Unclonable Functions In Reconfigurable Systems, Shrikant S. Vyas

Masters Theses

With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by FPGA-based encrypt/decrypt cores secured with secret keys. Physical unclonable functions (PUFs) use random manufacturing variations to generate outputs that can be used in keys. These outputs are specific to a chip and can be used to create device-tied secret keys. Due to reliability issues with PUFs, key generation with PUFs typically requires error correction techniques. This can result in substantial hardware costs. Thus, the total cost of a $n$-bit key far exceeds just the cost of …

Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men

Graduate Theses and Dissertations

The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced …

El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian

Computer Engineering

In today’s world of smartphones, self-driving cars, and internet-connected coffee makers, it seems as if computers are contained in everything around us. These “embedded systems” have become critical components of our lives, improving everything about the things they control, from cost, to speed, to simplicity. One area that embedded systems has hardly gained a foothold is in the world of floatbuilding. Most of the floats in the Tournament of Roses Parade, including the one built jointly by Cal Poly San Luis Obispo and Cal Poly Pomona, are technologically very simple, using mostly analog components and rudimentary discrete digital logic to …

A High Performance Advanced Encryption Standard (Aes) Encrypted On-Chip Bus Architecture For Internet-Of-Things (Iot) System-On-Chips (Soc), Xiaokun Yang

FIU Electronic Theses and Dissertations

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation.

Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state …