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On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman
On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report …