Electrical and Computer Engineering Commons^™

Efficient Edge Implementation Of Midasnet For Real-Time Depth Estimation In Indoor Robotics, Muhammed Yasi̇n Adiyaman, İsmai̇l Fai̇k Başkaya

Turkish Journal of Electrical Engineering and Computer Sciences

Real-time depth estimation is crucial in many vision-related tasks, including autonomous driving, 3D reconstruction, robotics, and simultaneous localization and mapping. In recent years, many methods have been proposed to solve depth maps from images by utilizing different modality setups like monocular vision, binocular vision, or sensor fusion. However, for real-time deployment on edge devices, complex methods are not suitable due to latency constraints and limited computation capacity. For edge implementation, models should be simple, minimal in size, and hardware-friendly. Considering these factors, we implemented MiDaSNet, which works on the simplest setup of monocular vision and utilizes hardware-friendly convolutional neural network-based …

A Study On Quantization And Hardware Cost Tradeoffs In A 5g Nr Ldpc Decoder On Fpga, Giancarlo Acosta

Master's Theses

The fixed-point implementation of a 5G New Radio LDPC decoder forces a tradeoff between precision and hardware cost, governed by the variable node word length W_L, the check node message width W_R, and the normalized min-sum correction factor α. This thesis characterizes how these three parameters affect both error correction performance and FPGA resource utilization for an LDPC decoder on an established LDPC decoder architecture. A bit-accurate MATLAB core model records bit error rate (BER) and frame error rate (FER) while a verified HDL Coder model generates synthesizable VHDL for Vivado synthesis, and both are swept …

Dot Product Engine Based Neuromorphic Hardware For Continuous-Time Biomedical Signal Classification, Sanjeev Srinivasan

Master's Theses

Accurate diagnosis of pathological conditions from biomedical signals, such as electrocardiograms (ECGs) is often performed offline, making it time-consuming, costly, and inefficient, especially when abnormal patterns are rare and long-term monitoring generates large amounts of data. To address this, this work proposes a compact, scalable, and programmable neuromorphic system designed for real-time preliminary arrhythmia detection and classification using ECG signals, that can be extended to other biomedical signals. The proposed design processes ECG signals using a delta modulation-based spike encoder, followed by classification with a dot-product engine (DPE) based spiking neural network (SNN) processor and winner-take-all (WTA) circuit. The architecture …

Domain-Specific Design On Fpga And Npu For Scientific Computing And On-Device Llm Inference, Miaoxiang Yu

All Dissertations

High-performance computing (HPC) is changing rapidly as scientific simulations and large language model (LLM) workloads push the need for higher performance under tight power and memory constraints. Conventional platforms such as CPUs and GPUs accelerate computation through instruction-driven parallelism, relying on multithreading, SIMD, and SIMT execution, but increasingly encounter scalability limits imposed by the power and memory walls. In contrast, Field-Programmable Gate Arrays (FPGAs) and Neural Processing Units (NPUs) offer a high-efficiency alternative through dataflow-oriented architectures that exploit deep pipelining and customized memory hierarchies to reduce data movement. However, the performance potential of these spatial accelerators remains largely unrealized when …

Design And Verification Of The Multi-Slit Solar Explorer Camera Field Programmable Gate Arrays, Jordan M. Johnson

All Graduate Reports and Creative Projects, Fall 2023 to Present

The Multi-Slit Solar Explorer, or MUSE, is a NASA mission that will take images of the Sun to study solar flares and the solar corona. The mission will provide insight into the mechanisms behind space weather. The mission consists of two cameras: the Spectrograph (SG), and the Context Imager (CI). The Utah State University Space Dynamics Laboratory is providing both cameras for the mission.

This report describes a part of the design and verification process for a central component on these cameras known as the Field Programmable Gate Arrays (FPGAs). These FPGAs are programmed to acquire, handle, and send images …

Design Of An Extensible And Scalable Data Acquisition System For Pulse Shape Discrimination, Prince John

McKelvey School of Engineering Graduate Student Theses & Dissertations

This thesis presents the design and development of a highly scalable, end-to-end data acquisition (DAQ) system for nuclear physics experiments that can be deployed in configurations ranging from a few to thousands of detector channels. The system is built as an extensible platform composed of modular 16-channel chipboards that support a wide range of scintillator and detector types and perform real-time, on-board data sparsification and pulse-shape processing. Three versions of the chipboard have been fabricated to date.

The DAQ architecture is based on a family of analog pulse-shape-processing application- specific integrated circuits (ASICs) developed by the IC Design Laboratory at …

A Low Power Fpga Compute Array For Machine Learning And Artificial Intelligence Applications, Todd Wilson

All Graduate Theses and Dissertations, Fall 2023 to Present

Modern small satellites often lack the ability to analyze their data in real time, relying instead on downlinking raw measurements to Earth before any scientific interpretation can occur. This delay restricts missions that require rapid awareness of environmental or space-weather events. This thesis presents the Low-power Array for Cubesat Edge Computing Architecture, Algorithms, and Applications (LACE-C3A), a hardware platform designed to enable in-orbit data processing within the power and volume limits of CubeSat-class spacecraft. 

LACE-C3A uses a modular cluster of flash-based FPGAs, which offer low power consumption, radiation resilience, and in-flight reconfigurability. The system consists of a Controller board responsible …

Flexible Fault-Tolerant Multi-Die Fpga-Based Architectures For Varying Space Environments, Yosof Ali Seif El Din Ali Maklad

Theses and Dissertations

It is well-known fact that spacecraft’s electronic components operate in an extreme harsh and varying space environments, beside changing orbit or passing through Van Allan Belts during orbital course results of radiation levels change. This thesis focuses on SRAM-based FPGA systems on-board of such spacecrafts, that are commonly utilized in space applications’ critical applications due to their capabilities and flexibility to reconfigure, since these systems are vulnerable to frequent negative impacts of ionizing radiation, thus inducing soft and hard errors leading to disastrous failures that could jeopardize the entire spacecraft. The soft errors’ effects are frequent yet can be mitigated, …

Lace Network Firmware: A Polarfire Fpga Network For Data Routing And Command Interfacing In Space Applications, Kade C. Howes

All Graduate Theses and Dissertations, Fall 2023 to Present

Modern small spacecraft rely on powerful yet efficient onboard compute devices to process data from sensors in real-time due to tight power and volume constraints. This work explores a new compute device system built from PolarFire Field-Programmable Gate Arrays (FPGAs), which are power-efficient, reprogrammable chips well-suited for space applications. The system connects via a central controller FPGA with one or multiple companion processing FPGAs, allowing sensor data to be quickly received and shared across the network. Standardized data formats and interfaces increase compatibility with spacecraft computers. By simplifying data handling and using high-speed communication links, this architecture makes it easier …

Fpga-Based Takagi-Sugeno Fuzzy Controller For Quadrotor Uav Stabilization And Trajectory Tracking, Hocine Khati, Mohamed Amine Nehmar, Arezki Fekik, Mohand Achour Touat, Hand Talem, Rabah Mellah

Turkish Journal of Electrical Engineering and Computer Sciences

This study presents the implementation of a fuzzy logic–based control system on a field-programmable gate array (FPGA) for a quadrotor autonomous aerial vehicle (UAV). The objective is to design and integrate six Takagi–Sugeno fuzzy controllers to regulate roll, pitch, and yaw angles, along with longitudinal, latitudinal, and altitude movements, thereby stabilizing the UAV and enabling it to follow a desired trajectory. Due to the computational complexity of the six controllers, achieving the desired performance requires considerable processing time, which can adversely affect the quadrotor’s mission. Owing to their high processing power and operating frequency, FPGAs enable the control algorithm to …

Reverse Engineering Bring Up And Profiling Of Multi-Fpga Systems, Henry A. Evans

Master's Theses

FPGAs have long been used for prototyping and verifying high-speed digital designs in industry and in academic research. As ASIC designs have grown in complexity and size, prototyping those designs on FPGAs has required multiple FPGAs that sometimes span multiple servers. Western Digital donated multiple FPGA-based systems to Cal Poly in 2023. These servers contain multiple high-end AMD FPGAs that are ideal for prototyping large high-speed digital designs, however the full documentation on how to use the servers and how the servers work was not provided. The servers did not come with any information on how to program the FPGAs, …

An Approach Of Implementing Mtncl And Mtd3l Asynchronous Logic Paradigms On Fpgas, Kile T. Harvey

Electrical Engineering and Computer Science Undergraduate Honors Theses

This thesis describes the creation of component libraries for the implementation of Multi-Threshold NULL Convention Logic (MTNCL) and Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD³L) on AMD 7 Series, AMD UltraScale, and AMD UltraScale+ FPGAs. The utilization of these libraries is identical to those used in the creation of MTNCL and MTD³L application-specific integrated circuits (ASICs), leading to intuitive use for designers familiar with the logic paradigms. Single-stage and pipelined designs were created using both libraries, which were then tested and verified to be logically equivalent to their ASIC counterparts. Future work will include creating and testing …

Adversarial Voltage Transients In Multi-Tenant Fpga Environments, Andrew J. Gerber

All Graduate Theses and Dissertations, Fall 2023 to Present

A Field Programmable Gate Array (FPGA) is a special type of computer chip that can be reconfigured to implement a nearly unlimited number of functions. Recent trends have led some companies to offer cloud-based FPGA solutions. Researchers are exploring how to properly secure multi-tenant environments where the designs from two or more customers are placed on the same FPGA with logical and spatial isolation, though multi-tenancy is not yet commercially available in cloud FPGAs. The digital circuits within an FPGA require a clock to synchronize timing within the design. The maximum speed that this clock can run at is determined …

A Parallel, Real-Time Fpga Implementation Of The Ccsds 123.0-B-2 Standard, Ruaa Ayman Saadi

Thesis/ Dissertation Defenses

Hyperspectral images are used in remote sensing scientific research and more, but they can reach hundreds of megabytes in size. This large number of datasets creates a problem with the limited storage capacity and bandwidth available on the satellite which in turn necessitates the use of hyperspectral image compression algorithms. The near lossless CCSDS123 hyperspectral algorithm provides a high compression capability, but it has some data dependencies in its predictor module that slows down the compression process. This Master of Science (MSc) thesis focuses on implementing a parallel, real-time FPGA based architecture of the near lossless CCSDS123 compression standard. The …

Performance Of Neural Networks On Fpga For Embedded Devices Using Hls4ml Framework, Alam N. Romo Lopez

Master's Theses

As machine learning models such as neural networks are investigated for their applications across many fields, the demand for models that can be implemented on an embedded device grows. Field Programmable Gate Arrays (FPGAs) have become an attractive option for implementing these models in hardware. This thesis considers the viability of FPGA implementations for machine learning on low-resourced embedded systems. The hls4ml project is a promising prospect for machine learning on FPGA devices. To test hls4ml, we used a model trained on the MNIST digits dataset, which was then synthesized for the PYNQ-Z2 device. We fine tuned the performance by …

Periodic Information Leakage Fault Detection On A Risc-V Microprocessor, Idris Somoye

Electrical and Computer Engineering ETDs

The execution behavior of a Microprocessor (μP) in the presence of a fault is difficult to predict because of the complex interactions across pipeline stages and between functional units within the architecture. Fault effects are known to not introduce any type of anomaly in the input-output behavior for 10s of thousands to millions of clock cycles. These characteristics increase the difficulty of evaluating μP architectures for resilience to information leakage events, i.e., scenarios where a fault causes sensitive data such as an encryption key to be inadvertently diverted to a primary output channel. This dissertation explores two promising strategies for …

Enhancing Fpga Synthesis For Space Applications: Performance Evaluation Of Scalehls In The Adapt Project, Ruoxi Wang

McKelvey School of Engineering Graduate Student Theses & Dissertations

This thesis investigates the application of ScaleHLS, a high-level synthesis (HLS) tool, to enhance Field-Programmable Gate Array (FPGA) synthesis for space applications, with a focus on the Antarctic Demonstrator Advanced Particle-astrophysics Telescope (ADAPT) project. The study explores how ScaleHLS optimizes the transformation of C code into FPGA-compatible designs to improve computational efficiency and resource utilization.

The research details the process of adapting ADAPT's computational algorithms for FPGA using ScaleHLS, emphasizing the tool's effectiveness in streamlining the code-to-hardware translation. A performance evaluation highlights significant improvements in resource management and operational speed, demonstrating the tool's impact on FPGA synthesis.

These findings illustrate …

Enabling On-Device Learning Through Hybrid Edge Computing Frameworks, Md Sharif Ahmed

Electrical Engineering Theses

In recent advancement of technology implementing Machine Learning (ML) algorithms with edge devices has gained remarkable popularity. Enabling Machine Learning (ML) in the edge opened new hybrid branch where edge hardware meets with Machine Learning (ML). Day by day devices are becoming more powerful and capable of doing a lot of computation. These powerful computational capabilities created the way of implementing Machine Learning (ML) on small edge devices. There are diverse ways we can implement machine learning models to the edge. For any embedded prototype, implementation of Tiny Machine Learning (TinyML) is making the IoT (Internet of Things) devices intelligent …

Analyzing A Software Based Lossy Compression Algorithm On An Fpga Platform, Tripp Herlong

All Theses

In HPC, the ability to generate data is outpacing our hardware capabilities of storing said data. This presents the need for compression so we can keep important data preserved without costly hardware upgrades or worrying about hardware speed limitations. Traditional forms of compression are software based, which presents a speed issue that can lead to bottlenecks when storing data.Scientific data lossy compression methods such as SZ enable a speedup on memory transfer by simplifying computation to minimize the essential data size. SZx is a lightweight version of the popular SZ floating point compressor that may benefit from hardware acceleration. This …

An Edge Computing System With Amd Xilinx Fpga Ai Customer Platform For Advanced Driver Assistance System, Tsun Kuang Chi, Tsung Yi Chen, Yu Chen Lin, Ting Lan Lin, Jun Ting Zhang, Cheng Lin Lu, Shih Lun Chen, Kuo Chen Li, Patricia Angela R. Abu

Department of Information Systems & Computer Science Faculty Publications

The convergence of edge computing systems with Field-Programmable Gate Array (FPGA) technology has shown considerable promise in enhancing real-time applications across various domains. This paper presents an innovative edge computing system design specifically tailored for pavement defect detection within the Advanced Driver-Assistance Systems (ADASs) domain. The system seamlessly integrates the AMD Xilinx AI platform into a customized circuit configuration, capitalizing on its capabilities. Utilizing cameras as input sensors to capture road scenes, the system employs a Deep Learning Processing Unit (DPU) to execute the YOLOv3 model, enabling the identification of three distinct types of pavement defects with high accuracy and …

Hardware Software Co-Design Of Zero-Knowledge Succinct Non-Interactive Argument Of Knowledge, Dev Shah, Allen Chellasamy

Electrical and Computer Engineering Senior Theses

Zero-Knowledge Succinct Non-interactive Argument of Knowledge (zk-SNARK) is an important security verification protocol in cryptography. However, zk-SNARK is a computationally expensive protocol in software, meaning that it takes a lot of time. In this paper, we focus on how we can increase the efficiency of the zk-SNARK protocol. The zk-SNARK protocol comprises of many algorithms put together. Our project focuses on optimizing one specific algorithm within the zk-SNARK protocol, the Number Theoretic Transform (NTT). We developed a hardware implementation of the NTT on a Field Programmable Gate Array (FPGA) board. To ensure the proper execution of the hardware, an external …

A Sindy Hardware Accelerator For Efficient System Identification On Edge Devices, Michael Sean Gallagher

Master's Theses

The SINDy (Sparse Identification of Non-linear Dynamics) algorithm is a method of turning a set of data representing non-linear dynamics into a much smaller set of equations comprised of non-linear functions summed together. This provides a human readable system model the represents the dynamic system analyzed. The SINDy algorithm is important for a variety of applications, including high precision industrial and robotic applications. A Hardware Accelerator was designed to decrease the time spent doing calculations. This thesis proposes an efficient hardware accelerator approach for a broad range of applications that use SINDy and similar system identification algorithms. The accelerator is …

Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays In Fpgas, Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy

Electrical and Computer Engineering Faculty Publications

Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply–Accumulate Array (SMA) as its computational brain. In this paper, we investigate the faulty output characterization of an SMA in a real silicon FPGA board. Experiments were run on a single Zybo Z7-20 board to control for process variation at nominal voltage and in small batches to control for temperature. The FPGA is rated up to 800 MHz in the data sheet due to the max frequency of the PLL, but the …

Field-Programmable Gate Array System-On-Chip Based Smart Home System, Jacques H. Ntahoturi

Graduate Research Theses & Dissertations

This thesis presents the design and implementation of a smart home system leveraging the Xilinx Kria FPGA SoC platform, which integrates FPGA flexibility with Arm Cortex processing capabilities. The system architecture incorporates a network of environmental sensors for real-time monitoring, an actuator network for control of home devices, and a security camera to safeguard the premises. The hardware design comprises an FPGA SoC module and a custom transition board, facilitating connectivity and integration with various devices. Firmware development utilized Xilinx Vivado for hardware description and Python for system applications, enabling efficient management of custom logic and communication protocols. The effectiveness …

A Novel Processor Architecture Implementing The Stacked Error Diffusion Algorithm And Its Zynq-Based Realization, Qishi Hu

Theses and Dissertations--Electrical and Computer Engineering

Digital halftoning reproduces continuous-tone images using patterns of black and white dots, while multitoning extends this concept by incorporating inks with intermediate intensities. These techniques are extensively utilized in the printing industry to accommodate the limited range of inks available in printers. Stacked error diffusion is a high-quality multitoning algorithm that adheres to the blue-noise dithering standard. This thesis research studies the potential parallelism inherent in the algorithm and introduces the design of a novel processor architecture optimized for efficient execution. The architecture is realized on an FPGA development board featuring a Zynq SoC. Additionally, the hardware prototype can also …

Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner

Faculty Publications

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Normalized Linearly-Combined Chaotic System: Design, Analysis, Implementation And Application, Md Sakib Hasan, Anurag Dhungel, Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain

Faculty and Student Publications

This work presents a general framework for developing a multi-parameter 1-D chaotic system for uniform and robust chaotic operation across the parameter space. This is important for diverse practical applications where parameter disturbance may cause degradation or even complete disappearance of chaotic properties. The wide uninterrupted chaotic range and improved chaotic properties are demonstrated with the aid of stability analysis, bifurcation diagram, Lyapunov exponent (LE), Kolmogorov entropy, Shannon entropy, and correlation coefficient. We also demonstrate the proposed system’s amenability to cascading for further performance improvement. We introduce an efficient Field-Programmable Gate Array (FPGA)-based implementation and validate its chaotic properties using …

Development Of The Digital Signal Processing For The Space Weather Probes Version 2 Sensor Using The Matlab/Simulink Environment, Benjamin J. Lewis

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Space Weather Probes (SWP) is an instrument that provides measurements of the plasma environment of the ionosphere. SWP was flown on the Scintillation Prediction Observation Task (SPORT) mission, a joint mission between the United States of America and Brazil. This thesis will develop the digital signal processing (DSP) hardware design for the Space Weather Probes version 2 (SWP2). The data from these instruments will be used to determine the density and temperature of the local plasma, as well as the electric field in the local plasma. This thesis presents the design and testing of the DSP designs for all of …