Electrical and Computer Engineering Commons^™

Degradation Specific Ocr, Subramaniam Venkatraman

Boise State University Theses and Dissertations

Optical Character Recognition (OCR) is the mechanical or electronic translation of scanned images of handwritten, typewritten, or printed text into machine-encoded text. OCR has many applications, such as enabling a text document in a physical form to be editable, or enabling computer searching on a computer of a text that was initially in printed form. OCR engines are widely used to digitize text documents so that they can be digitally stored for remote access, mainly for websites. This facilitates the availability of these invaluable resources instantly, no matter the geographical location of the end user. Huge OCR misclassification errors can …

A Study Of The Lyapunov Stability Of An Open-Loop Induction Machine, Ahmed Oteafy, John Chiasson

Electrical and Computer Engineering Faculty Publications and Presentations

The induction motor is widely utilized in industry and exists in a plethora of applications. Until the last 20 years or so, it was primarily used in an open-loop fashion (i.e., balanced sinusoidal voltages, constant load torque and viscous friction) with its inherent stability counted on to allow operation over a wide range of operating conditions. Unlike classical arguments based on the steady-state torque-slip curve, a rigorous analytical stability argument using the full nonlinear dynamical model is presented. In particular, conditions for global asymptotic stability of the induction motor in the sense of Lyapunov are given in terms of the …

Cavity Resonant Mode In A Metal Film Perforated With Two-Dimensional Triangular Lattice Hole Arrays, Wan Kuang, Alex English, William B. Knowlton, Jeunghoon Lee, William L. Hughes, Bernard Yurke

Electrical and Computer Engineering Faculty Publications and Presentations

The transmission property of metallic films with two-dimensional hole arrays is studied experimentally and numerically. For a triangular lattice subwavelength hole array in a 150 nm thick Ag film, both cavity resonance and planar surface modes are identified as the sources of enhanced optical transmissions. Semi-analytical models are developed for calculating the dispersion relation of the cavity resonant mode. They agree well with the experimental results and full-wave numerical calculations. Strong interaction between the cavity resonant mode and surface modes is also observed.

Silver Chalcogenide Based Memristor Devices, Antonio S. Oblea, Achyut Timilsina, David Moore, Kristy A. Campbell

Electrical and Computer Engineering Faculty Publications and Presentations

We have fabricated two-terminal chalcogenide-based devices containing Ge₂Se₃ and Ag that function as memristors. These devices have been electrically characterized at room temperature using quasi-static DC methods, AC sinusoidal methods, and AC pulse testing methods. In all cases, the devices exhibit memristive behavior.

Joint Loop End Modeling Improves Covariance Model Based Non-Coding Rna Gene Search, Jennifer Smith

Electrical and Computer Engineering Faculty Publications and Presentations

The effect of more detailed modeling of the interface between stem and loop in non-coding RNA hairpin structures on efficacy of covariance-model-based non-coding RNA gene search is examined. Currently, the prior probabilities of the two stem nucleotides and two loop-end nucleotides at the interface are treated the same as any other stem and loop nucleotides respectively. Laboratory thermodynamic studies show that hairpin stability is dependent on the identities of these four nucleotides, but this is not taken into account in current covariance models. It is shown that separate estimation of emission priors for these nucleotides and joint treatment of substitution …

Synthesis Of Higher-Order K-Delta-1-Sigma Modulators For Wideband Adcs, Vishal Saxena, R. Jacob Baker

Electrical and Computer Engineering Faculty Publications and Presentations

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method.

Indirect Compensation Techniques For Three-Stage Fully-Differential Op-Amps, Vishal Saxena, R. Jacob Baker

Electrical and Computer Engineering Faculty Publications and Presentations

As CMOS technology continues to evolve, the
supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology …

Differentially Encoded Quadrature Phase Shift Key Communication And Real-Time Implementation, Robert Walton Conant

Boise State University Theses and Dissertations

Robust communication methods are integral to advances in modern technology. Software defined radios (SDRs) have been the chief instruments of communication for the last three decades. Upcoming generations of wireless networks and phone systems depend on successful implementations of increasingly sophisticated software defined modulation methods. The challenges presented by encoding, modulation, signal conditioning, timing, and decision algorithms are non-trivial. Adapting to the impacts of wired and wireless channels adds further complexity.

While not comprehensive on the subject of communications, this text serves to introduce the practical concepts of binary communications, modulation methods, the digital signal processor (DSP), and software defined …

A Reconfigurable Pattern Matching Hardware Implementation Using On-Chip Ram-Based Fsm, Nader I. Rafla, Indrawati Gauba

Electrical and Computer Engineering Faculty Publications and Presentations

The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. In this paper, a reconfigurable hardware implementation for pattern matching using Finite State machine (FSM) is proposed. The FSM design is RAMbased and is reconfigured on the fly through altering memory contents only. An embedded processor is used for orchestrating run time …

Software Defined Radio: Inexpensive Hardware And Software Tools, Thad B. Welch, Cameron H. G. Wright, Michael G. Morrow

Electrical and Computer Engineering Faculty Publications and Presentations

DSP topics such as software defined radio are more easily taught if appropriate demonstrations and laboratory experiences are provided. This paper describes a new, inexpensive software defined radio educational platform based upon MATLAB and the Texas Instruments C6713 digital signal processing starter kit. We describe the hardware and software issues and briefly describe recommended classroom use.

Compact Method For Modeling And Simulation Of Memristor Devices: Ion Conductor Chalcogenide-Based Memristor Devices, Kristy A. Campbell, Antonio Oblea, Achyut Timilsina

Electrical and Computer Engineering Faculty Publications and Presentations

A compact model and simulation methodology for chalcogenide based memristor devices is proposed. From a microprocessor design view point, it is important to be able to simulate large numbers of devices within the integrated circuit architecture in order to speed up reliably the development process. Ideally, device models would accurately describe the characteristic device behavior and would be represented by single-valued equations without requiring the need for recursive or numerically intensive solutions. With this in mind, we have developed an empirical chalcogenide compact memristor model that accurately describes all regions of operations of memristor devices employing single-valued equations.

An Analysis Of Binarization Ground Truthing, Elisa H. Barney Smith

Electrical and Computer Engineering Faculty Publications and Presentations

The accuracy of a binarization algorithm is often calculated relative to a ground truth image. Except for synthetically generated images, no ground truth image exists. Evaluating binarization on real images is preferred. The ground truthing between and among different operators is compared. Four direct metrics were used. The variability of the results of five different automatic binarization algorithms were compared to that of manual ground truth results. Significant variability in the ground truth results was found.

Case Study Of Finite Resource Optimization In Fpga Using Genetic Algorithm, Jingxia Wang, Sin Ming Loo

Electrical and Computer Engineering Faculty Publications and Presentations

Modem Field-Programmable Gate Arrays (FPGAs) are becoming very popular in embedded systems and high performance applications. FPGA has benefited from the shrinking of transistor feature size, which allows more on-chip reconfigurable (e.g., memories and look-up tables) and routing resources available. Unfortunately, the amount of reconfigurable resources in a FPGA is fixed and limited. This paper investigates the mapping scheme of the applications in a FPGA by utilizing sequential processing (e.g., Altera Nios II or Xilinx Microblaze, using C programming language) and task specific hardware (using hardware description language). Genetic Algorithm is used in this study. We found that placing sequential …

Optimizing Reconfigurable Hardware Resource Usage In System-On-A-Programmable-Chip With Location-Aware Genetic Algorithm, Sin Ming Loo, Jingxia Wang

Electrical and Computer Engineering Faculty Publications and Presentations

This paper presents static task scheduling using location-aware genetic algorithm techniques to schedule task systems to finite amounts of reconfigurable hardware. This research optimizes the use of limited reconfigurable resources. This scheduling algorithm is built upon our previous work [12- 14]. In this paper, the genetic algorithm has been expanded to include a feature to assign selected tasks to specific functional units. In this reconfigurable hardware environment, multiple sequential processing elements (soft core processors such as Xilinx MicroBlaze [22] or Altera Nios-II [1]), task-specific core (application specific hardware), and communication network within the reconfigurable hardware can be used (such a …

Computation Intelligence Method To Find Generic Non-Coding Rna Search Models, Jennifer A. Smith

Electrical and Computer Engineering Faculty Publications and Presentations

Fairly effective methods exist for finding new noncoding RNA genes using search models based on known families of ncRNA genes (for example covariance models). However, these models only find new members of the existing families and are not useful in finding potential members of novel ncRNA families. Other problems with family-specific search include large processing requirements, ambiguity in defining which sequences form a family and lack of sufficient numbers of known sequences to properly estimate model parameters. An ncRNA search model is proposed which includes a collection of non-overlapping RNA hairpin structure covariance models. The hairpin models are chosen from …

High-Voltage Programmable Delta-Sigma Modulation Voltage-Control Circuit, Lucien Jan Bissey

Boise State University Theses and Dissertations

Modern memory semiconductors require different internal voltages to accomplish the myriad of tasks that are required for operation. These internal voltages are multiples of the external voltage that is applied to the part. This multiple can be greater than one, as is the case with voltage pumps, less than one, as in the case of regulated supplies, and negative, as in the case of negative charge pumps. All of these potentials require control and regulation to ensure proper operation of the die. The control of the supply ensures that the required potentials are available when the die needs it. The …

Gain And Offset Error Correction For Cmos Image Sensor Using Delta-Sigma Modulation, Kuang Ming Yap

Boise State University Theses and Dissertations

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. These benefits include lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADCs are required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset errors in the ADC's transfer function. These errors will lead to fixed-pattern noise. Correcting gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. …

K-Delta-1-Sigma Modulators For Wideband Analog-To-Digital Conversion, Vishal Saxena

Boise State University Theses and Dissertations

As CMOS technology scales, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes a first-order K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared integrator and K-quantizing feedback paths and can potentially achieve significantly higher conversion bandwidths when compared to the traditional …

Gain Error Correction For Cmos Image Sensor Using Delta-Sigma Modulation, Kuangming Yap, R. Jacob Baker

Electrical and Computer Engineering Faculty Publications and Presentations

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. This includes lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADC is required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset error in its transfer function, which will lead to fix pattern noise. Correcting these gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. Therefore, …

Main Memory With Proximity Communication: A Wide I/O Dram Architecture, Qawi Harvard, R. Jacob Baker, Robert Drost

Electrical and Computer Engineering Faculty Publications and Presentations

The bandwidth and power consumption of dynamic random access memory (DRAM), used as the main memory of a computer system, impacts computer execution rates. DRAM manufacturers focus on density increases, due to the innate price per bit decline of main memory, while processor manufacturers continually focus on boosting performance. This leads to a performance gap between the two technologies. Proximity communication promises to increase the off/on chip bandwidth of DRAM products while reducing the power consumption of the main memory system. The design of a memory system employing 4 Gb DRAM chips with a 64-bit wide communication bus using proximity …

Influence Of Cu Diffusion Conditions On The Switching Of Cu-Sio2-Based Resistive Memory Devices, S.C. Puthen Thermadam, S. K. Bhagat, T. L. Alford, Y. Sakaguchi, M. N. Kozicki, Maria Mitkova

Electrical and Computer Engineering Faculty Publications and Presentations

This paper presents a study of Cu diffusion at various temperatures in thin SiO₂ films. Film composition and diffusion products were analyzed using Secondary Ion Mass Spectroscopy, Rutherford Backscattering Spectrometry, X-ray Diffraction and Raman Spectroscopy methods. We found a strong dependence of the diffused Cu concentration, which varied between 0.8 at.% and 10^-3 at.%, on the annealing temperature. X-ray diffraction and Raman studies revealed that Cu does not react with the SiO2 network and remains in elemental form after diffusion. Programmable Metallization Cell (PMC) resistive memory cells were fabricated with these Cu-diffused SiO₂ films as the active …

Relating Electrophotographic Printing Model And Is013660 Standard Attributes, Elisa H. Barney Smith

Electrical and Computer Engineering Faculty Publications and Presentations

A mathematical model of the electrophotographic printing process has been developed. This model can be used for analysis. From this a print simulation process has been developed to simulate the effects of the model components on toner particle placement. A wide variety of simulated prints are produced from the model's three main inputs, laser spread, charge to toner proportionality factor and toner particle size. While the exact placement of toner particles is a random process, the total effect is not. The effect of each model parameter on the ISO 13660 print quality attributes line width, fill, raggedness and blurriness is …

2x1d Image Registration And Comparison, Geng Zheng, Elisa H. Barney Smith, Nader Rafla, Tim Andersen

Electrical and Computer Engineering Faculty Publications and Presentations

This paper presents a novel 2x1D phase correlation based image registration method for verification of printer emulator output. The method combines the basic phase correlation technique and a modified 2x1D version of it to achieve both high speed and high accuracy. The proposed method has been implemented and tested using images generated by printer emulators. Over 97% of the image pairs were registered correctly, accurately dealing with diverse images with large translations and image cropping.

Effect Of Pre-Processing On Binarization, Elisa Barney Smith, Laurence Likforman-Sulem, Jérôme Darbon

Electrical and Computer Engineering Faculty Publications and Presentations

The effects of different image pre-processing methods for document image binarization are explored. They are compared on five different binarization methods on images with bleed through and stains as well as on images with uniform background speckle. The binarization method is significant in the binarization accuracy, but the pre-processing also plays a significant role. The Total Variation method of pre-processing shows the best performance over a variety of pre-processing methods.

Atomic Force Microscopy Of Dna Self-Assembled Nanostructures For Device Applications, Hieu Bui, Craig Onodera, Bernard Yurke, Elton Graugnard, Wan Kuang, Jeunghoon Lee, William B. Knowlton, William L. Hughes

Electrical and Computer Engineering Faculty Publications and Presentations

DNA nanotechnology, which relies on Watson-Crick hybridization, is a versatile selfassembly process whereby a variety of complex nanostructures can be fabricated with sublithographic features.[1] Adopting this technology, 1012 identical devices can be synthesized to have hundreds of components with 1nm resolution. Example nanostructures include: 1) DNA motifs [2], 2) two-dimensional DNA crystals [3], and DNA origami [4]. Currently, this technology is being adopted towards electronic, optical, and opto-electronic devices.[5]

Wide I/O Dram Architecture Utilizing Proximity Communication, Qawi Ibnzayd Harvard

Boise State University Theses and Dissertations

The bandwidth and power consumption of dynamic random access memory, used as the main memory of a computer system, impacts the computer’s execution rate even with the existence of a memory hierarchy. DRAM manufacturers focus on density increases due to the innate price per bit decline of main memory while processor manufacturers continually focus on boosting performance by increasing the number of instructions completed per second. This leads to a performance gap between the microprocessor and DRAM.

Proximity communication promises to increase the I/O density of DRAM products while reducing the power consumption of the main memory system. This thesis …

New Metric Describes Edge Noise In Bilevel Images, Elisa H. Barney Smith

Electrical and Computer Engineering Faculty Publications and Presentations

A new approach enables quantitative and qualitative characterization of varying edge noise even if the additive noise level is constant.

Evolution Of Chemical Structure During Silver Photodiffusion Into Chalcogenide Glass Thin Films, A. Kovalskiy, H. Jain, Maria Mitkova

Electrical and Computer Engineering Faculty Publications and Presentations

The change of chemical structure resulting after X–ray and photo-induced silver diffusion into chalcogenide glass (ChG) thin films is monitored by high resolution X-ray photoelectron spectroscopy (XPS). As₄₀S₆₀ and Ge₃₀Se₇₀ thin films, which are based on pyramids and tetrahedral structural units, are investigated as model materials. Survey, core level (As 3d, S 2p, Ge 3d, Ge 2p, Se 3d, Ag 3d_5/2, O 1s, C 1s) and valence band spectra have been recorded and analyzed. Reference point for the …

Compact Optical Curvature Sensor With A Flexible Microdisk Laser On A Polymer Substrate, Wan Kuang, M. H. Shih, K. S. Hsu, Y. C. Yang, Y. C. Wang, S. K. Tsai, Y. C. Liu, Z. C. Chang, M. C. Wu

Electrical and Computer Engineering Faculty Publications and Presentations

In this paper, a chip-scale compact optical curvature sensor was demonstrated. It consists of a low threshold InGaAsP microdisk laser on a flexible polydimethylsiloxane polymer substrate. The curvature dependence of lasing wavelength was characterized by bending the cavity at different bending radii. The measurements showed that the lasing wavelength decreases monotonously with an increasing bending curvature. A good agreement between experiment and three-dimensional finite-difference time-domain simulation was also obtained. The sensitivity of the compact device to the bending curvature is -23.7 nm/mm form the experiment.

Indirect Compensation Techniques For Three-Stage Cmos Op-Amps, Vishal Saxena, R. Jacob Baker

Electrical and Computer Engineering Faculty Publications and Presentations

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain …