Hardware Systems Commons^™

Development Of A Cubesat Payload To Model Particle Dampening In Space: Design And Implementation Of Software For Cp7, Daniel Walker

Computer Engineering

The California Polytechnic State University CubeSat student research & development group, PolySat, is currently in a mature development stage of a single unit CubeSat designated CP7. The CP7 mission implements a scientific payload designed to characterize particle dampers in microgravity conditions. When subjected to vibration, the momentum exchanges and frictional forces of the particles create a damping effect that can be optimized to suit a number of applications over a broad frequency and amplitude range. In space based applications, particle dampers would serve as a robust and simple device to eliminate jitter in optical assemblies and other sensitive instrumentation. This …

Data Routing In Multicore Processors Using Dimension Increment Method, Arpita H. Kadakia

UNLV Theses, Dissertations, Professional Papers, and Capstones

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource.

In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, …

Fault-Injection Experiment For The Statistical Characterization Of Faults In Avionics Communication System, Amy M. Yates

Electrical & Computer Engineering Theses & Dissertations

Since flight control systems perform safety-critical functions, it is important to understand the possible effects on the closed-loop dynamical system's performance caused by these faults. The purpose of this project is to design the software and hardware needed to add fault-injection and monitoring capabilities to ROBUS-2, a flight communication system. ROBUS-2 is the current version of the fault-tolerant computer communication system used by the Scalable Processor-Independent Design for Enhanced Reliability (SPIDER), a general-purpose fault-tolerant integrated modular architecture (IMA) developed at the NASA Langley Research Center. The major components of SPIDER include processing elements (PEs) to perform calculations, bus interface units …

The Executable Command In Support Of Scheduled Subroutine Calls, Andrew Scott Lewis

Electrical & Computer Engineering Theses & Dissertations

A potential solution to improving the utilization of increased thread level parallelism available in modern general purpose CPU's is the inclusion of a hardware scheduler. The hardware scheduler is designed to schedule subroutine calls based on a numerical condition in a high performance memory located on the CPU die, due to which the size of available memory is extremely limited. The main stumbling block in the development of a feasible hardware scheduler is the lack of a method of invoking a scheduled call using a single pointer. The use of a single pointer allows the limited size of the memory …

Nexys 2 Slot Machine, Mark Luna

Computer Engineering

No abstract provided.

Ultrasonic Shark-Tag Locator System For Iver2 Auv, Nathaniel Garcia

Computer Engineering

The purpose of this project is to develop a system for tracking an ultrasonic underwater transmitter that can be integrated into an IVER2 AUV to allow it to follow and monitor tagged sharks in the ocean for scientific research.

The system consists of a four main components including a shark-tag, two hydrophones, a filter/amplifier & threshold detector circuit, and a microcontroller.

This project, while not completing field testing and integration with the IVER2, is a proof of concept of a system that utilizes passive sonar to determine a bearing from the system to a shark-tag transmitter. Additionally, it devised several …

A Low Power Touch Screen Document Viewer, Chris Perfetto

Computer Engineering

This document will cover the requirements, design, implementation and testing of a low power touch screen document viewer to serve as a replacement bulletin board. It was Implemented using a BeagleBoard development board, a 4.3” touchscreen LCD and a SD card with a Ubuntu Linux OS installed. The testing of this device is primarily testing the power consumption. The device is not yet complete and will require further development for it to completely satisfy the requirements.

Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci

Computer Engineering

Digital media players often include a visualization component that allows a user to watch a visualization synchronized to their music or videos. This project uses the visualization plugin API of an existing media playback program (WinAmp) but it displays its visuals using physical LED lights. Instead of outputting visuals to the computer screen, data is sent over USB to a micro controller that runs the LED lights. This project aims to give users a more visceral visual experience than traditional visualizations on the computer screen.

Global Positioning Logger, Matthew Hall

Computer Engineering

The Global Positioning Logger (GPL) is a mobile embedded device that utilizes GPS technology. The GPS data is used to display current speed and past global locations.

Utopia 3.0: Power Cycling Controller Board, Allan Chan

Computer Engineering

The Universal Test & Observation Power Interface Adapter (UTOPIA) is a device used for hard drive testing by Western Digital. Utopia is designed to provide an interface to communicate with a hard drive and perform power cycling functions on a hard drive.

The purpose of this project is to develop a prototype that retains the features of the previous Utopia boards while including two new features to be used in the next design: voltage margining and improved Serial Input/Output (SIO) drive control.

This document describes the design of version 3.0 of UTOPIA starting with component selection, schematic design and, PCB …

Super Special Codes Using Super Matrices, Florentin Smarandache, W.B. Vasantha Kandasamy, K. Ilanthenral

Branch Mathematics and Statistics Faculty and Staff Publications

The new classes of super special codes are constructed in this book using the specially constructed super special vector spaces. These codes mainly use the super matrices. These codes can be realized as a special type of concatenated codes. This book has four chapters. In chapter one basic properties of codes and super matrices are given. A new type of super special vector space is constructed in chapter two of this book. Three new classes of super special codes namely, super special row code, super special column code and super special codes are introduced in chapter three. Applications of these …

Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski

Department of Electrical Engineering and Computer Science - Daytona Beach

This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented.