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Full-Text Articles in Hardware Systems
Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young
Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young
Theses and Dissertations
We develop a methodology for formalizing, verifying, and validating the requirements specification of real-time systems based on a graphical and formal hierarchical Finite State Machine (FSM) language Reacto. We define a means to quantify time and express real-time constraints in Reacto and a transformation from Reacto to the Very High Speed Integrated Circuit (VHSIC) hardware Description Language (VHDL). Reacto's high level abstractions, graphical nature, and theorem prover produce efficient, accurate, and easily understood specifications. We use VHDL's event driven simulation capability, concurrency, and temporal operators to thoroughly examine temporal dependencies between the state machine transitions, and to increase simulation power …
A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin
A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin
Theses and Dissertations
Model-based reasoning permits diagnostic applications to be written without waiting for someone to become an 'expert' of the system. For model-based diagnostics, there must be a model to reason from. This thesis explores using a VHDL description of the system as that model. A system based around a VHDL interpreter was written specifically for a model-based diagnostic algorithm. Currently, the diagnostic system uses an algorithm by Dries. This algorithm was derived from Scarl's Full Consistency Algorithm. The system was designed to be modular so that different diagnostic techniques could be implemented. It is divided into three parts: a VHDL parser, …