Hardware Systems Commons^™

Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru

Electrical & Computer Engineering Theses & Dissertations

Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging …

Fault-Injection Experiment For The Statistical Characterization Of Faults In Avionics Communication System, Amy M. Yates

Electrical & Computer Engineering Theses & Dissertations

Since flight control systems perform safety-critical functions, it is important to understand the possible effects on the closed-loop dynamical system's performance caused by these faults. The purpose of this project is to design the software and hardware needed to add fault-injection and monitoring capabilities to ROBUS-2, a flight communication system. ROBUS-2 is the current version of the fault-tolerant computer communication system used by the Scalable Processor-Independent Design for Enhanced Reliability (SPIDER), a general-purpose fault-tolerant integrated modular architecture (IMA) developed at the NASA Langley Research Center. The major components of SPIDER include processing elements (PEs) to perform calculations, bus interface units …

The Executable Command In Support Of Scheduled Subroutine Calls, Andrew Scott Lewis

Electrical & Computer Engineering Theses & Dissertations

A potential solution to improving the utilization of increased thread level parallelism available in modern general purpose CPU's is the inclusion of a hardware scheduler. The hardware scheduler is designed to schedule subroutine calls based on a numerical condition in a high performance memory located on the CPU die, due to which the size of available memory is extremely limited. The main stumbling block in the development of a feasible hardware scheduler is the lack of a method of invoking a scheduled call using a single pointer. The use of a single pointer allows the limited size of the memory …

A Modular Kernel Linear Discriminant Analysis Of Gabor Features For Improved Face Recognition, Neeharika Gudur

Electrical & Computer Engineering Theses & Dissertations

Automatic face recognition is one of the major challenges in computer vision and pattern analysis. This thesis presents an efficient face recognition system that is robust with regards to changes in illumination, facial expressions and partial occlusions. Modular Kernel Linear Discriminant Analysis performed on Gabor Features obtained from the face images is employed for improving face recognition accuracy. A face image is pre-processed using the 2D Gabor wavelet transform to achieve invariance to illumination in images. Modular approaches that divide the pre-processed images into smaller sub-images provide improved accuracy, as the facial variations in an image are confined to local …

Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal

Electrical & Computer Engineering Theses & Dissertations

This thesis describes research in automated methods for the recognition of human faces. The research is driven by the need to design a method, which would ensure high accuracy under the conditions of facial expression, illumination and pose variations. The resulting method is able to cope with uncontrolled nature of facial expression, illumination and head rotations. The main novelty of this work is the idea that some of the local facial features do not vary even when the facial expression, illumination and pose vary. This idea is applied to the existing principle component analysis lPCA) method to arrive at a …

A Pipelined Architecture For Real Time Correction Of Barrel Distortion In Wide-Angle Camera Images, Hau Trung Ngo

Electrical & Computer Engineering Theses & Dissertations

Images captured by wide-angle cameras show barrel type spatial distortion due to wide-angle configuration of the camera lens where image regions farther from the center are compressed in a nonlinear fashion. The barrel distortion correction technique based on least squares estimation attempts to correct a distorted image by expanding it nonlinearly so that straight lines in the object space remain straight in the image space. The intensity value of a pixel in the expanded image is calculated by back mapping its position to the corresponding position in the distorted image and performing linear interpolation on the neighboring pixels. Distorted images …

Studies Related To The Design And Implementation Of A Magnetic Suspension And Balance System, Syed Adeel Akhtar Jafri

Electrical & Computer Engineering Theses & Dissertations

This thesis presents studies related to the magnetic suspension and balance system (MSBS) of the Princeton/ONR High Reynolds Number Testing Facility (HRTF). The main motivation for developing the MSBS is to provide interference free aero/hydrodynamic testing of submersible models, which will lead to more accurate measurements. From the controls point of view, the main specification of the MSBS is to robustly control the position of a submersible model in five degrees of freedom (DOF), including three translational as well as pitching and yawing positions. The MSBS should not only regulate the submersible model's position but should also allow for small …

Speech Feature Computation For Visual Speech Articulation Training, Stefan Auberg

Electrical & Computer Engineering Theses & Dissertations

A new version of the Visual Speech Articulation Training Aid was implemented which provides real-time visual feedback for speech articulation training. This version was migrated to a Windows Multimedia PC from a previous version which used a Personal Computer (PC) system and additional specialized and expensive custom hardware. This new version will make the system more available to schools and private users. A new method was developed for computing spectral/temporal features which characterize the speech sounds. In addition to the typical frame-based spectral analysis parameters, the new method represents temporal changes of the spectrum with a small number of features. …

Simulator For Concurrent Processing Data Flow Architectures, Mahyar R. Malekpour

Electrical & Computer Engineering Theses & Dissertations

A software simulator capable of simulating execution of an algorithm graph on a given system under the Algorithm To Architecture Mapping Model (ATAMM) rules is presented in this thesis. ATAMM is capable of modeling the execution of large-grained algorithms on distributed data flow architectures. Investigating the behavior and determining the performance of an ATAMM based system requires the aid of software tools. The ATAMM Simulator presented in this thesis is capable of determining the behavior, performance, and reliability of a system without having to build a hardware prototype. Case studies are performed on four algorithms to demonstrate the capabilities of …

Analog Computer Simulation With Automatic Scaling By Digital Computer, Mark Anthony Motter

Electrical & Computer Engineering Theses & Dissertations

A computer-aided design approach for the simplification of analog computer simulation is presented. The simulation configuration consists of an EAI 2000 analog computer with serial communications link to a PDP — 11/24 digital computer. Under control of the PDP-11, the analog simulations are realized with appropriate time and magnitude scaling which adjusts the range of the simulation coefficients and prevents overloads of the analog components. The analog computer hardware configuration accommodates both stable plants up to eighth order and closed-loop systems up to tenth order. Cascade compensation is provided for the closed-loop systems.

The plant may be described by either …