Hardware Systems Commons^™

Fail-Safe Logic Design Strategies Within Modern Fpga Architectures, Priya A. Bhakta

Electrical and Computer Engineering ETDs

Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced single event upsets (SEUs) and fault injection attacks, requiring the use of redundancy techniques such as fail-safe computing. Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. This work investigates circuit-level techniques and implements fail-safe computing processes as mitigation for SEUs and fault injection attacks on FPGAs. The analysis reveals vulnerabilities that exist in FPGAs over those in application-specific integrated circuits (ASIC); thus, requiring a more elaborate network of redundant circuits and checking logic. The reconfiguration capability of FPGAs adds complexity to fail-safe …

Cyber Physical Systems For Non-Contact Infrastructure Monitoring, Roya Nasimi

Civil Engineering ETDs

In recent decades, the decay of infrastructure has become a relevant challenge of both developed and under developing countries. Prioritization of maintenance and repairs of transportation infrastructure is a new worldwide priority since it is important to quantify the rate of decay of assets to increase both safety and cost-efficient operations. Infrastructure owners need frequent inspections on their assets to predict and to avoid unsafe conditions prone to cause disasters. Frequent infrastructure inspections call for cost-effective methods. Traditional measurement methods require human access to the infrastructure, are subjective, expensive, and unsafe. Therefore, infrastructure managers are interested in exploring new non-contact …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …

Side-Channel Power Resistance For Encryption Algorithms Using Implementation Diversity, Ivan M. Bow

Electrical and Computer Engineering ETDs

This thesis paper investigates countermeasures to hardware side-channel attacks and proposes a new solution to this ever growing threat against data integrity and security. The side-channel attack methods, differential power analysis and correlation power analysis, are both very powerful techniques and are used to gain access to secrets inside of a field programmable gate array that are otherwise inaccessible, in particular the cryptographic key for the Advanced Encryption Standard algorithm. To counter these attacks, we propose a method of changing the internal hardware configuration of the field programmable gate array using dynamic partial reconfiguration. Using this method, we change the …

Nonlinear Least Squares 3-D Geolocation Solutions Using Time Differences Of Arrival, Michael V. Bredemann

Mathematics & Statistics ETDs

This thesis uses a geometric approach to derive and solve nonlinear least squares minimization problems to geolocate a signal source in three dimensions using time differences of arrival at multiple sensor locations. There is no restriction on the maximum number of sensors used. Residual errors reach the numerical limits of machine precision. Symmetric sensor orientations are found that prevent closed form solutions of source locations lying within the null space. Maximum uncertainties in relative sensor positions and time difference of arrivals, required to locate a source within a maximum specified error, are found from these results. Examples illustrate potential requirements …

Criticality Assessments For Improving Algorithmic Robustness, Thomas B. Jones

Computer Science ETDs

Though computational models typically assume all program steps execute flawlessly, that does not imply all steps are equally important if a failure should occur. In the "Constrained Reliability Allocation" problem, sufficient resources are guaranteed for operations that prompt eventual program termination on failure, but those operations that only cause output errors are given a limited budget of some vital resource, insufficient to ensure correct operation for each of them.

In this dissertation, I present a novel representation of failures based on a combination of their timing and location combined with criticality assessments---a method used to predict the behavior of systems …

Erasure Techniques In Mrd Codes, Florentin Smarandache, W.B. Vasantha Kandasamy, R. Sujatha, R.S. Raja Durai

Branch Mathematics and Statistics Faculty and Staff Publications

In this book the authors study the erasure techniques in concatenated Maximum Rank Distance (MRD) codes. The authors for the first time in this book introduce the new notion of concatenation of MRD codes with binary codes, where we take the outer code as the RD code and the binary code as the inner code. The concatenated code consists of the codewords of the outer code expressed in terms of the alphabets of the inner code. These new class of codes are defined as CRM codes. This concatenation techniques helps one to construct any CRM code of desired minimum distance …

Super Special Codes Using Super Matrices, Florentin Smarandache, W.B. Vasantha Kandasamy, K. Ilanthenral

Branch Mathematics and Statistics Faculty and Staff Publications

The new classes of super special codes are constructed in this book using the specially constructed super special vector spaces. These codes mainly use the super matrices. These codes can be realized as a special type of concatenated codes. This book has four chapters. In chapter one basic properties of codes and super matrices are given. A new type of super special vector space is constructed in chapter two of this book. Three new classes of super special codes namely, super special row code, super special column code and super special codes are introduced in chapter three. Applications of these …