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Articles 31 - 37 of 37
Full-Text Articles in Hardware Systems
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Theses and Dissertations
Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts …
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Theses and Dissertations
A Parallel Discrete Event Simulation Coprocessor was designed to off- load the synchronization overhead from the processors executing the application. In a multiprocessor architecture, one coprocessor executes the synchronization routines for each host processor. Speedup can be achieved when the host processor executes the application and the coprocessor concurrently executes synchronization routines. The coprocessor uses a programmable microcode control store to guarantee flexibility in the synchronization routines. The coprocessor uses an Extreme Search Associative Memory to support fast Next Event Queue NEQ management. This associative memory uses bit-serial word-parallel search logic to provide 01 insert and retrieval time of events …
A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton
A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton
Theses and Dissertations
The dissertation develops a decision criteria to select an associative-memory organization that minimizes the execution time of a mix of associative-search operations and a decision criteria to estimate the layout dimensions of each organization for a specified memory size. The dissertation reclassifies Feng's associative-search operations into three hardware-influenced categories: bit-position independent (BPI), record-content independent (RCI); bit-position dependent (BPD), RCI; and BPD, record-content dependent (RCD). It develops a relationship between the categories and three associative-memory organizations: the CAM, the bit-serial word-parallel associative memory (BSWPAM) , and the extreme-search associative memory (ESAM). A version of the CAM, three versions of the BSWPAM, …
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Theses and Dissertations
A hardware discrete event simulation (DES) coprocessor was designed to eliminate synchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design …
Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young
Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young
Theses and Dissertations
We develop a methodology for formalizing, verifying, and validating the requirements specification of real-time systems based on a graphical and formal hierarchical Finite State Machine (FSM) language Reacto. We define a means to quantify time and express real-time constraints in Reacto and a transformation from Reacto to the Very High Speed Integrated Circuit (VHSIC) hardware Description Language (VHDL). Reacto's high level abstractions, graphical nature, and theorem prover produce efficient, accurate, and easily understood specifications. We use VHDL's event driven simulation capability, concurrency, and temporal operators to thoroughly examine temporal dependencies between the state machine transitions, and to increase simulation power …
A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin
A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin
Theses and Dissertations
Model-based reasoning permits diagnostic applications to be written without waiting for someone to become an 'expert' of the system. For model-based diagnostics, there must be a model to reason from. This thesis explores using a VHDL description of the system as that model. A system based around a VHDL interpreter was written specifically for a model-based diagnostic algorithm. Currently, the diagnostic system uses an algorithm by Dries. This algorithm was derived from Scarl's Full Consistency Algorithm. The system was designed to be modular so that different diagnostic techniques could be implemented. It is divided into three parts: a VHDL parser, …
Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.
Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.
Theses and Dissertations
An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements …