Hardware Systems Commons^™

Increasing Efficiency In Boundary Security With Wireless Sensor Networks And Geospatial Information Systems Using Homology Theory, Luis Berumen^, Eric Chaidez^, Hamide Dogan*, Jose Gerardo Rosiles**

COURI Symposium Abstracts, Spring 2011

As part of an institutional investigation, we attempt to address the challenges the US customs and Border protection agency faces in the El Paso region. Our research focuses on defining a system for the surveillance application, and the use of mathematical models employed to achieve a greater efficiency of such architecture. With the use of the defined system, we apply homology theory through the algebraic process of topology, to accomplish an independent coordinate-free based system, which covers the surveillance area, with lesser quantity of sensor nodes. Our architecture makes the use of an operating system for wireless sensor networks; TinyOS, …

Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg

Theses and Dissertations

Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …

Global Positioning Logger, Matthew Hall

Computer Engineering

The Global Positioning Logger (GPL) is a mobile embedded device that utilizes GPS technology. The GPS data is used to display current speed and past global locations.

Where Does Your Institution Stand?, Wendell Brase, Mark Askren

Information Technology Services: Publications

Media coverage of sustainability and "green" issues is hard to ignore these days. But less clear is a specific understanding of what this agenda means within higher ed IT organizations. For starters, it's useful to self-assess whether your campus is a leading innovator on all things "green" or satisfied to remain inconspicuous in the middle of the pack. If your institution is trailing but wants to assert a leadership role in environmental stewardship, you need to get engaged to understand what it will take to catch up and how IT can be a leader, not just a contributor, to such …

Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal

Electrical & Computer Engineering Theses & Dissertations

This thesis describes research in automated methods for the recognition of human faces. The research is driven by the need to design a method, which would ensure high accuracy under the conditions of facial expression, illumination and pose variations. The resulting method is able to cope with uncontrolled nature of facial expression, illumination and head rotations. The main novelty of this work is the idea that some of the local facial features do not vary even when the facial expression, illumination and pose vary. This idea is applied to the existing principle component analysis lPCA) method to arrive at a …

Rekabentuk Perkakasan Khas Ecc (Reed-Solomon), Muhamad Mursid Noorizan

Student Works (2000-2009)

Dokumen ini disiapknn bagi menyediakan laporan tentang perjalanan projek perkakasan khas ECC yang dijalankan. Bahagian pertama dokumen ini terdapat pengenalan tentang projek. Bahagian kedua pula menyatakan tentang kajian yang telah dilakukan bagi memilih kod-kod pembetulan yang ingin dibangunkan. Seterusnya pada bahagian tiga, dinyatakan serba sedikit tentang bahasa yang digunakan dalam pembangunan projek iaitu VHDL. Sahagian keempat pula menceritakan tentang senibina-senibina dan rekabentuk-rekabentuk perkakasan khas. Dalam bahagian lima, dokumen menceritakan tentang fasa pembangunan yang telah dijalankan. Bahagian enam dan tujuh pula menceritakan tentang perbincangan dan kesimpulan daripada projek yang telah dijalankan.

Keyboard - Smart Card Reader Controller Using Vhdl, Lani Mohd Zuwairi

Student Works (2000-2009)

As the time fly by the technology of computers has improves and much security is needed in every transaction of data that being done. In this project, designing a microcontroller for keyboard and smart card reader terminal integration is being done. At first stage, the architecture of the controller will analyze and studied. This will need some practice of knowledge in computer organization and architecture, as well as microprocessors architecture designs. Then the architecture is design using hardware prototyping. This is by using the VHSIC Hardware Description Language (VHDL). The codes done using the language then being simulate to get …

Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor

Student Works (2000-2009)

Tesis ini menghuraikan sebuah pendarab titik apungan 32bit bertalian paip 18MHz yang direkabentuk menggunakan bahasa perihalan perkakasan YHDL, peralatan sintesis Synopsys FPGA Express dan ·peralatan pemetaan Xilinx Alliance, PTA ini menggunakan 1007 CLB dan 100 10B di mana peranti pemetaan yang digunakan ialah xc4036xl-bg432-2 daripada pustaka XC4000 Xilinx FPGA. Pendarab ini mengandungi tiga tahap talian paip yang belainan fungsi. Tahap pertama melaksanakan penjanaan dedarab dan penambahan dedarab secara carry save dan penambahan eksponen. la menggunakan algoritma Booth tertib kedua dan pepohon Wallace dengan pemampat 4-2. Tahap kcdua pula melakukan penambahan bawaan rambatan akhir, penormalan mantisa dan pembetulan eksponen manakala tahap …

Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani

Student Works (2000-2009)

ALU testing mechanism using Boundary Scan technique is a project which is develop to be the tester for testing the digital circuit, integrated circuit and computer chip. The goal of this project is to develop a mechanism and as well building an ALU chip so that we will able to test and determine whether the chips are in a good shape and condition. This project contains two parts: one is lo develop an ALU and second is to develop the boundary scan chip. ALU is a unit or a component for a cligital circuit or a integrated circuit which is …

Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain

Computer Science and Engineering Research

An important stage in circuit design is placement, where components are assigned to physical locations on a chip. A popular contemporary approach for placement is the use of simulated annealing. While this approach has been shown to produce good placement solutions, recent work in genetic algorithms has produced promising results. The purpose of this study is to determine which approach will result in better placement solutions.

A simplified model of the placement problem, circuit partitioning, was tested on three circuits with both a genetic algorithm and a simulated annealing algorithm. When compared with simulated annealing, the genetic algorithm was found …

Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp

Theses and Dissertations

Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …

A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh

Computer Science: Faculty Publications and Other Works

This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.