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Articles 31 - 39 of 39

Full-Text Articles in Digital Circuits

Selfish Wavelength Assignment In Multifiber Optical Networks, Evangelos Bampas, Aris Pagourtzis, George Pierrakos, Katerina Potika Apr 2008

Selfish Wavelength Assignment In Multifiber Optical Networks, Evangelos Bampas, Aris Pagourtzis, George Pierrakos, Katerina Potika

Faculty Publications, Computer Science

No abstract provided.

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Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran Oct 2003

Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran

Electrical & Computer Engineering Theses & Dissertations

CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm to compute values of trigonometric, logarithmic and transcendental functions by performing vector rotations, which can be implemented with only shift and add operations in a digital system. CORDIC algorithms are extensively used in the areas of digital signal processing, digital image processing and artificial neural networks. A new technique, named unidirectional CORDIC, for efficient computation of trigonometric and hyperbolic functions is presented in this thesis. In the conventional CORDIC algorithm, the vector rotations are performed in both clockwise and counterclockwise directions, but in the unidirectional CORDIC the vectors are rotated only …

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An Analysis Of A Private-Key Cryptosystem, Wei-Wey Tan Jan 2002

An Analysis Of A Private-Key Cryptosystem, Wei-Wey Tan

Student Works (2000-2009)

In this dissertation, we have presented a new block cipher. The proposed block cipher is a Substitution-Permutation network cryptosystem with a block length of 128 bits and key length of 256 bits. With the increased key length and block size, the proposed block cipher has greater security over DES. A modular design approach was applied. The cipher has three major building blocks and their interaction has been carefully chosen to achieve better security and performance. Algorithmic S­-Boxes are used to provide confusion and nonlinearity in the cipher. The proposed cipher uses a highly diffusive diffusion layer, which is a combination …

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A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris Jan 2002

A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris

Student Works (2000-2009)

No abstract provided.

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Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine Jan 2000

Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine

Student Works (2000-2009)

Projek Ilmiah Tahap Akhir II, iaitu WXES 3182 adalah suatu latihan akademik di dalam penyelidikan, rekabentuk, pembangunan dan komunikasi yang melibatkan prinsip-prinsip sains komputer. Projek WXES 3182 ini merupakan kursus pelengkap bagi pelajar-pelajar tahun akhir untuk mendapatkan penganugerahan Sarjana Muda Sains Komputer. Projek WXES 3182 ini adalah kesinabungan daripada projek WXES 3181 Kajian penyehdikan yang telah dijalankan adalah berkaitan dengan konsep sistem nombor reja dan litar aritmetik reja. Laporan latihan ilmiah tahap akhir II ini, merangkumi pembangunan projek WXES 3181 dan WXES 3182. laporan ini terdiri daripada lapan bahagian dan diantaranya ialah pengenalan kepada projek, kajian literasi, metodologi yang digunakan …

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Vhdl Description For Ip Engine, Bathich Zeliall Jan 2000

Vhdl Description For Ip Engine, Bathich Zeliall

Student Works (2000-2009)

Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol …

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Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec Mar 1992

Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec

Theses and Dissertations

The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …

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Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau Dec 1991

Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau

Theses and Dissertations

VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …

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Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor Mar 1991

Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor

Theses and Dissertations

The ultimate purpose of this research is to reduce the time needed for execution of parallel computer simulations. In particular, the impact of task assignment strategies is determined for parallel VHDL circuit simulations. The classical scheduling problem, which assigns n precedence-constrained tasks to m processors is NP-complete in all but the simplest cases. The problem of assigning simulation tasks is further complicated by the iterative nature of computer simulations: each task is required to execute multiple times as the simulation executes. This investigation develops a polynomial-time algorithm (the level strategy) which provides optimal assignment for iterative systems with specific constraints. …

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