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Articles 31 - 33 of 33
Full-Text Articles in Digital Circuits
Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec
Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec
Theses and Dissertations
The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …
Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau
Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau
Theses and Dissertations
VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …
Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor
Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor
Theses and Dissertations
The ultimate purpose of this research is to reduce the time needed for execution of parallel computer simulations. In particular, the impact of task assignment strategies is determined for parallel VHDL circuit simulations. The classical scheduling problem, which assigns n precedence-constrained tasks to m processors is NP-complete in all but the simplest cases. The problem of assigning simulation tasks is further complicated by the iterative nature of computer simulations: each task is required to execute multiple times as the simulation executes. This investigation develops a polynomial-time algorithm (the level strategy) which provides optimal assignment for iterative systems with specific constraints. …