Computer and Systems Architecture Commons^™

Demystifying Hardware Formal Verification For Undergraduate Education: A Risc-V Processor Case Study With Coursework Implementation, Riley A. Peters

Master's Theses

Hardware verification engineers apply formal methods to prove that a digital device always behaves according to its specification. This differs from traditional functional verification, in which engineers establish correctness by repeatedly sending test inputs to the device and comparing the outputs against a reference model. With the growing complexity of integrated circuits, the demand for digital verification engineers with formal methods experience has continued to increase. However, California Polytechnic State University: San Luis Obispo's current curriculum lacks dedicated material to prepare students for these roles.

This thesis seeks to address the lack of formal methods material through two efforts. First, …

The Risc-V Fpga (Rvfpga) Teaching Package, Daniel Chaver, Sarah Harris, Luis Pinuel, Olof Kindgren, Zubair Kakakhel, Chris Owen, Jose I. Gomez-Perez, Fernando Castro, Katzalin Olcoz, Julio Villalba-Moreno, Alexander Grinshpun, Freddy Gabbay, Luke Seed, Rui Duarte, Manuel Lopez, Oscar Alonso, Robert Owen

Electrical & Computer Engineering Faculty Research

RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related …

Confidential, Attestable, And Efficient Inter-Cvm Communication With Arm Cca, Sina Abdollahi, Amir Al Sadi, Marios Kogias, Hamed Haddadi, David Kotz

Other Faculty Materials

Confidential Virtual Machines (CVMs) are increasingly adopted to protect sensitive workloads from privileged adversaries such as the hypervisor. While they provide strong isolation guarantees, existing CVM architectures lack first-class mechanisms for inter-CVM data sharing due to their disjoint memory model, making inter-CVM data exchange a performance bottleneck in compartmentalized or collaborative multi-CVM systems. Under this model, a CVM's accessible memory is either shared with the hypervisor or protected from both the hypervisor and all other CVMs. This design simplifies reasoning about memory ownership; however, it fundamentally precludes plaintext data sharing between CVMs because all inter-CVM communication must pass through hypervisor-accessible …

Digital Simulations Of Memristors Towards Integration With Reconfigurable Computing, Ivris Raymond

Computer Science and Computer Engineering Undergraduate Honors Theses

The end of Moore’s Law has been predicted for decades. Demand for increased parallel computational performance has been increased by improvements in machine learning. This past decade has demonstrated the ever-increasing creativity and effort necessary to extract scaling improvements in CMOS fabrication processes. However, CMOS scaling is nearing its fundamental physical limits. A viable path for increasing performance is to break the von Neumann bottleneck. In-memory computing using emerging memory technologies (e.g. ReRam, STT, MRAM) offers a potential path beyond the end of Moore’s Law. However, there is currently very little support from industry tools for designers wishing to incorporate …

An Optimized And Scalable Blockchain-Based Distributed Learning Platform For Consumer Iot, Zhaocheng Wang, Xueying Liu, Xinming Shao, Abdullah Alghamdi, Md. Shirajum Munir, Sujit Biswas

School of Cybersecurity Faculty Publications

Consumer Internet of Things (CIoT) manufacturers seek customer feedback to enhance their products and services, creating a smart ecosystem, like a smart home. Due to security and privacy concerns, blockchain-based federated learning (BCFL) ecosystems can let CIoT manufacturers update their machine learning (ML) models using end-user data. Federated learning (FL) uses privacy-preserving ML techniques to forecast customers' needs and consumption habits, and blockchain replaces the centralized aggregator to safeguard the ecosystem. However, blockchain technology (BCT) struggles with scalability and quick ledger expansion. In BCFL, local model generation and secure aggregation are other issues. This research introduces a novel architecture, emphasizing …

Analyzing Microarchitectural Residue In Various Privilege Strata To Identify Computing Tasks, Tor J. Langehaug

Theses and Dissertations

Modern multi-tasking computer systems run numerous applications simultaneously. These applications must share hardware resources including the Central Processing Unit (CPU) and memory while maximizing each application’s performance. Tasks executing in this shared environment leave residue which should not reveal information. This dissertation applies machine learning and statistical analysis to evaluate task residue as footprints which can be correlated to identify tasks. The concept of privilege strata, drawn from an analogy with physical geology, organizes the investigation into the User, Operating System, and Hardware privilege strata. In the User Stratum, an adversary perspective is taken to build an interrogator program that …

Identification Of Return-Oriented Programming Attacks Using Risc-V Instruction Trace Data, Daniel F. Koranek, Scott R. Graham, Brett J. Borghetti, Wayne C. Henry

Faculty Publications

An increasing number of embedded systems include dedicated neural hardware. To benefit from this specialized hardware, deep learning techniques to discover malware on embedded systems are needed. This effort evaluated candidate machine learning detection techniques for distinguishing exploited from non-exploited RISC-V program behavior using execution traces. We first developed a dataset of execution traces containing Return Oriented Programming (ROP) exploitation on the RISC-V Instruction Set Architecture (ISA) and then developed several deep learning bidirectional Long Short-Term Memory (LSTM) models capable of distinguishing exploited traces from non-exploited traces, each using subsets of features from the execution traces. An objective of this …

Otter Vector Extension, Alexis A. Peralta

Computer Engineering

This paper offers an implementation of a subset of the "RISC-V 'V' Vector Extension", v0.7.x. The "RISC-V 'V' Vector Extension" is the proposed vector instruction set for RISC-V open-source architecture. Vectors are inherently data-parallel, allowing for significant performance increases. Vectors have applications in fields such as cryptography, graphics, and machine learning. A vector processing unit was added to Cal Poly's RISC-V multi-cycle architecture, known as the OTTER. Computationally intensive programs running on the OTTER Vector Extension ran over three times faster when compared to the baseline multi-cycle implementation. Memory intensive applications saw similar performance increases.

On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.

Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …

Evaluating The Presence Of A Victim Cache On An Arm Processor, Lakshmi Vidya Peri

Computer Science Graduate Projects and Theses

Mobile processor is a CPU designed to save power. It is found in mobile computers and cell phones. A CPU chip, designed for portable computers, is typically housed in a smaller chip package, but more importantly, in order to run cooler, it uses lower voltages than its desktop counterpart and has more "sleep mode" capability. A mobile processor can be throttled down to different power levels and/or sections of the chip can be turned off entirely when not in use. ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA). The relative simplicity of ARM processors makes …

Nato Human View Architecture And Human Networks, Holly A. H. Handley, Nancy P. Houston

Engineering Management & Systems Engineering Faculty Publications

The NATO Human View is a system architectural viewpoint that focuses on the human as part of a system. Its purpose is to capture the human requirements and to inform on how the human impacts the system design. The viewpoint contains seven static models that include different aspects of the human element, such as roles, tasks, constraints, training and metrics. It also includes a Human Dynamics component to perform simulations of the human system under design. One of the static models, termed Human Networks, focuses on the human-to-human communication patterns that occur as a result of ad hoc or deliberate …

Research Poster: Survey Of Environmental Data Portals: Features And Characteristics, David Walker

2010 Annual Nevada NSF EPSCoR Climate Change Conference

Research poster

Tailored Systems Architecture For Design Of Space Science And Technology Missions Using Dodaf V2.0, Nicholas J. Merski

Theses and Dissertations

The use of systems architecture, following a set of integrated descriptions from an architecture framework, has been well codified in Department of Defense acquisition and systems engineering. However, in the Space Science and Technology (S&T) community, this guidance and practice is not commonly adopted. This paper outlines an approach to leverage the changes made in DoD Architecture Framework 2.0 (DoDAF2.0), and the renewed emphasis on data and support to acquisition decision analysis. After decomposing the Space S&T design lifecycle into phases, design milestones and activities using process models, a set of DoDAF prescribed and Fit-for-Purpose views are constructed into a …

Methodology For Value-Driven Enterprise Architecture Development Goals: Application To Dodaf Framework, Justin W. Osgood

Theses and Dissertations

The Department of Defense Architectural Framework (DoDAF) describes 29 distinct views but offers limited guidance on view selection to meet system needs. This research extends the Value-Driven Enterprise Architecture Score (VDEA-Score) from a descriptive, evaluation protocol toward a prescriptive one by evaluating each DoDAF view and its contribution to the overall objective of the completed architecture. This extension of VDEA is referred to as VDEA-Development Goals (VDEA-DG). The program manager or other decision-makers may use this insight to justify the allocation of resources to the development of specific architecture views considered to provide maximum value. This research provides insight into …

Dynamic Task Prediction For An Spmt Architecture Based On Control Independence, Komal Jothi

Dissertations and Theses

Exploiting better performance from computer programs translates to finding more instructions to execute in parallel. Since most general purpose programs are written in an imperatively sequential manner, closely lying instructions are always data dependent, making the designer look far ahead into the program for parallelism. This necessitates wider superscalar processors with larger instruction windows. But superscalars suffer from three key limitations, their inability to scale, sequential fetch bottleneck and high branch misprediction penalty. Recent studies indicate that current superscalars have reached the end of the road and designers will have to look for newer ideas to build computer processors.

Speculative …

What Should Be In A Human Behavior Representation Federation Object Model For High Level Architecture, Gurkan Haznedaroglu

Electrical & Computer Engineering Theses & Dissertations

Modeling and Simulation (M&S) can assist in evaluating scenarios and enhancing the performance of operational systems. Fully integrated use of MBS can enable the evaluation of the effectiveness of proposed equipment or software in realistic simulated environments and can provide an assessment of the impacts of specific equipment or capabilities on battle outcomes. Every level, from strategic planners, technology experts, operations research analysts, weapons systems designers and users, testers, maintainers, and cost analysts, has to be interactively involved to maximize the benefits of this approach. Human behavior is a very important part of the M&S process. Especially in constructive simulations, …

Exploring Hardware Based Primitives To Enhance Parallel Security Monitoring In A Novel Computing Architecture, Stephen D. Mott

Theses and Dissertations

This research explores how hardware-based primitives can be implemented to perform security-related monitoring in real-time, offer better security, and increase performance compared to software-based approaches. In doing this, we propose a novel computing architecture, derived from a contemporary shared memory architecture, that facilitates efficient security-related monitoring in real-time, while keeping the monitoring hardware itself safe from attack. This architecture is flexible, allowing security to be tailored based on the needs of the system. We have developed a number of hardware-based primitives that fit into this architecture to provide a wide array of monitoring capabilities. A number of these primitives provide …

Fault And Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices, George R. Roelke Iv

Theses and Dissertations

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a "fault and defect tolerant" (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required …

Creating Enterprise Simulations Using High Level Architecture, Anton R. Lidums

Electrical & Computer Engineering Theses & Dissertations

Despite an established need, there are two remaining roadblocks to building distributed simulations and enterprise simulation systems. First, commercial simulation packages and engineering modeling tools are not readily distributable across multiple computers and have traditionally had very little impetus for utilizing a distributable format. Second, although HLA simulations have been built and there are tools to facilitate those efforts, very little has been done or written that specifically describes a "non-standard" integration implementation in sufficient detail to make the process reusable or repeatable. This thesis introduces a proof of concept prototype that was developed to integrate simulations. The paper presents …

A Reconfigurable Superscalar Architecture, Christopher B. Mayer

Theses and Dissertations

The invention of the Field Programmable Gate Array (FPGA) has led to a number of interesting developments. One is the idea of providing custom hardware support for applications running on a computer. These reconfigurable computers have been shown to decrease the execution time for some applications. Based on past results, attention has subsequently turned to using reconfigurable computing in general-purpose computers (e.g. desktop and workstation environments). This thesis develops a design for just such a computer. The design, FPGADLX, is based on a hypothetical superscalar computer running the DLX instruction set and is generic enough in principle to be adapted …

A Toolkit For Specializing Production Operating System Code, Crispin Cowan, Dylan Mcnamee, Andrew P. Black, Calton Pu, Jonathan Walpole, Charles Krasic, Perry Wagle, Qian Zhang

Computer Science Faculty Publications and Presentations

Specialization has been recognized as a powerful technique for optimizing operating systems. However, specialization has not been broadly applied beyond the research community because the current techniques, based on manual specialization, are time-consuming and error-prone. This paper describes a specialization toolkit that should help broaden the applicability of specializing operating systems by assisting in the automatic generation of specialized code, and {\em guarding} the specialized code to ensure the specialized system continues to be correct. We demonstrate the effectiveness of the toolkit by describing experiences we have had applying it in real, production environments. We report on our experiences with …

Design And Implementation Of High-Radix Arithmetic Systems Based On The Sdnr/Rns Data Representation, Paul Whyte

Theses : Honours

This project involved the design and implementation of high-radix arithmetic systems based on the hybrid SDNRIRNS data representation. Some real-time applications require a real-time arithmetic system. An SDNR/RNS arithmetic system provides parallel, real-time processing. The advantages and disadvantages of high-radix SDNR/RNS arithmetic, and the feasibility of implementing SDNR/RNS arithmetic systems in CMOS VLSI technology, were investigated in this project. A common methodological model, which included the stages of analysis, design, implementation, testing, and simulation, was followed. The combination of the SDNR and RNS transforms potential complex logic networks into simpler logic blocks. It was found that when constructing a SDNRIRNS …

A Study Of Dynamic Optimization Techniques: Lessons And Directions In Kernel Design, Calton Pu, Jonathan Walpole

Computer Science Faculty Publications and Presentations

The Synthesis kernel [21,22,23,27,28] showed that dynamic code generation, software feedback, and fine-grain modular kernel organization are useful implementation techniques for improving the performance of operating system kernels. In addition, and perhaps more importantly, we discovered that there are strong interactions between the techniques. Hence, a careful and systematic combination of the techniques can be very powerful even though each one by itself may have serious limitations. By identifying these interactions we illustrate the problems of applying each technique in isolation to existing kernels. We also highlight the important common under-pinnings of the Synthesis experience and present our ideas on …

Creating And Manipulating Formalized Software Architectures To Support A Domain-Oriented Application Composition System, Cynthia G. Anderson

Theses and Dissertations

This research investigated technology which enables sophisticated users to specify, generate, and maintain application software in domain-oriented terms. To realize this new technology, a development environment, called Architect, was designed and implemented. Using canonical formal specifications of domain objects, Architect rapidly composes these specifications into a software application and executes a prototype of that application as a means to demonstrate its correctness before any programming language specific code is generated. Architect depends upon the existence of a formal object base (or domain model) which was investigated by another student in related research. The research described in this thesis relied on …

An Intelligent Real-Time System Architecture Implemented In Ada, Michael A. Whelan

Theses and Dissertations

Conventional real-time systems are fully deterministic allowing for off-line, optimal, task scheduling under all circumstances. Real-time intelligent systems add non-deterministic task execution times and non- deterministic task sets for scheduling purposes. Non-deterministic task sets force intelligent real-time systems to trade-off execution time with solution quality during run-time and perform dynamic task scheduling. Four basic design considerations addressing those tradeoffs have been identified: control reasoning, focus of attention, parallelism, and algorithm efficacy. Non-real- time intelligent systems contain an environment sensor, a model of the environment, a reasoning process, and a large collection of procedural processes. Real-time intelligent systems add to these …

Smimd - A Synchronous Multiple Instruction Multiple Data Computer Architecture, Cathy C. Roberts

Computer Science Theses & Dissertations

This thesis assesses the feasibility of utilizing a hypercube interconnect topology to link a heterogeneous processor array in a very long instruction word (VLIW) computer architecture. The research focused upon the selection of a suitable arrangement of processors for the computer and the subsequent demonstration of the architecture's capability to handle simple loop iterations. Previous attempts at VLIW computer design are summarized, the new SMIMD architecture is presented, and suggestions for future research are given. The thesis concludes with results of the initial performance evaluations of the architecture design.

A Software Design Tool For Predictable Performance In Real-Time, Data Flow Architectures, Brij Mohan V. Mandala

Electrical & Computer Engineering Theses & Dissertations

A software design tool which aids in the performance evaluation and selection of operating points for an algorithm implemented in ATAMM defined data flow architectures is presented in this thesis. ATAMM (Algorithm To Architecture Mapping Model) is a new graph theoretic model developed by researchers at Old Dominion University and the NASA-Langley Research Center. ATAMM is capable of modeling the execution of large-grained algorithms on distributed data flow architectures. A software tool is required for predicting the performance, determining the resource requirements and for selecting suitable operating points for an ATAMM based system. The ATAMM Design Tool presented in this …

Parallel Architectures For Solving Combinatorial Problems Of Logic Design, Phuong Minh Ho

Dissertations and Theses

This thesis presents a new, practical approach to solve various NP-hard combinatorial problems of logic synthesis, logic programming, graph theory and related areas. A problem to be solved is polynomially time reduced to one of several generic combinatorial problems which can be expressed in the form of the Generalized Propositional Formula (GPF) : a Boolean product of clauses, where each clause is a sum of products of negated or non-negated literals.

Software Tools For Performance Evaluation Of Concurrent Processing, Rodrogo A. Obando

Electrical & Computer Engineering Theses & Dissertations

The development and use of software tools for performance evaluation of concurrent processing is presented in this thesis. The particular concurrent processing architecture proposed by Stoughton and Mielke is investigated. The modelling of this architecture is based on Petri net theory and it can be studied making use of circuit theory. Computation of lower bounds for Time Between Outputs (TBO) and Time Between Input and Output (TBIO) can be accomplished by using principles of circuit theory, among others. This new modelling needs to be deeply evaluated and studied. This evaluation and study is accomplished with the tools developed and presented …