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Computer and Systems Architecture Commons™
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- Peer-to-peer architecture (Computer networks) (5)
- Computer networks (4)
- Computer simulation (3)
- Electronic data processing--Distributed processing (3)
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- Simulation (3)
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- Distributed operating systems (Computers) (2)
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- CMP (1)
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Articles 1 - 11 of 11
Full-Text Articles in Computer and Systems Architecture
The Risc-V Fpga (Rvfpga) Teaching Package, Daniel Chaver, Sarah Harris, Luis Pinuel, Olof Kindgren, Zubair Kakakhel, Chris Owen, Jose I. Gomez-Perez, Fernando Castro, Katzalin Olcoz, Julio Villalba-Moreno, Alexander Grinshpun, Freddy Gabbay, Luke Seed, Rui Duarte, Manuel Lopez, Oscar Alonso, Robert Owen
The Risc-V Fpga (Rvfpga) Teaching Package, Daniel Chaver, Sarah Harris, Luis Pinuel, Olof Kindgren, Zubair Kakakhel, Chris Owen, Jose I. Gomez-Perez, Fernando Castro, Katzalin Olcoz, Julio Villalba-Moreno, Alexander Grinshpun, Freddy Gabbay, Luke Seed, Rui Duarte, Manuel Lopez, Oscar Alonso, Robert Owen
Electrical & Computer Engineering Faculty Research
RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related …
A P2p Computing System For Overlay Networks, Grzegorz Chmaj, Krzysztof Walkowiak
A P2p Computing System For Overlay Networks, Grzegorz Chmaj, Krzysztof Walkowiak
Electrical & Computer Engineering Faculty Research
A distributed computing system is able to perform data computation and distribution of results at the same time. The input task is divided into blocks, which are then sent to system participants that offer their resources in order to perform calculations. Next, a partial result is sent back by the participants to the task manager (usually one central node). In the case when system participants want to get the final result, the central node may become overloaded, especially if many nodes request the result at the same time. In this paper we propose a novel distributed computation system, which does …
Heuristic Algorithms For Optimization Of Task Allocation And Result Distribution In Peer-To-Peer Computing Systems, Grzegorz Chmaj, Krzysztof Walkowiak, Michal Tarnawski, Michal Kucharzak
Heuristic Algorithms For Optimization Of Task Allocation And Result Distribution In Peer-To-Peer Computing Systems, Grzegorz Chmaj, Krzysztof Walkowiak, Michal Tarnawski, Michal Kucharzak
Electrical & Computer Engineering Faculty Research
Recently, distributed computing system have been gaining much attention due to a growing demand for various kinds of effective computations in both industry and academia. In this paper, we focus on Peer-to-Peer (P2P) computing systems, also called public-resource computing systems or global computing systems. P2P computing systems, contrary to grids, use personal computers and other relatively simple electronic equipment (e.g., the PlayStation console) to process sophisticated computational projects. A significant example of the P2P computing idea is the BOINC (Berkeley Open Infrastructure for Network Computing) project. To improve the performance of the computing system, we propose to use the P2P …
Location Of Processor Allocator And Job Scheduler And Its Impact On Cmp Performance, Dawid Zydek, Grzegorz Chmaj, Alaa Shawky, Henry Selvaraj
Location Of Processor Allocator And Job Scheduler And Its Impact On Cmp Performance, Dawid Zydek, Grzegorz Chmaj, Alaa Shawky, Henry Selvaraj
Electrical & Computer Engineering Faculty Research
High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and …
Decision Strategies For A P2p Computing System, Grzegorz Chmaj, Krzysztof Walkowiak
Decision Strategies For A P2p Computing System, Grzegorz Chmaj, Krzysztof Walkowiak
Electrical & Computer Engineering Faculty Research
Peer-to-Peer (P2P) computing (also called ‘public-resource computing’) is an effective approach to perform computation of large tasks. Currently used P2P computing systems (e.g., BOINC) are most often centrally managed, i.e., the final result of computations is created at a central node using partial results – what may be not efficient in the case when numerous participants are willing to download the final result. In this paper, we propose a novel approach to P2P computing systems. We assume that results can be delivered to all peers in a distributed way using three types of network flows: unicast, Peer-to-Peer and anycast. We …
Software Development Approach For Discrete Simulators, Grzegorz Chmaj, Dawid Maksymilian Zydek
Software Development Approach For Discrete Simulators, Grzegorz Chmaj, Dawid Maksymilian Zydek
Electrical & Computer Engineering Faculty Research
Simulation is the most common approach to perform the problem research. Among several types of simulation, the most common way is the discrete simulation, which assumes the division of the time scale into fixed length time slots. Depending on investigated problem, simulation packages may be used or it could be necessary to design and create own simulation system. In this paper, we propose the complete pre-study scheme and the most commonly appearing implementation problems with suggested solutions. We also describe how to implement the exemplary simulator in C++.
Random Approach To Optimization Of Overlay Public-Resource Computing Systems, Grzegorz Chmaj, Krzysztof Walkowiak
Random Approach To Optimization Of Overlay Public-Resource Computing Systems, Grzegorz Chmaj, Krzysztof Walkowiak
Electrical & Computer Engineering Faculty Research
The growing need for computationally demanding systems triggers the development of various network-oriented computing systems organized in a distributed manner. In this work we concentrate on one kind of such systems, i.e. public-resource computing systems. The considered system works on the top of an overlay network and uses personal computers and other relatively simple electronic equipment instead of supercomputers. We assume that two kinds of network flows are used to distribute the data in the public-resource computing systems: unicast and peer-to-peer. We formulate an optimization model of the system. After that we propose random algorithms that optimize jointly the allocation …
Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang
Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang
Electrical & Computer Engineering Faculty Research
ue to its simplicity and scalability, the differentiated services (DiffServ) model is expected to be widely deployed across wired and wireless networks. Though supporting DiffServ scheduling algorithms for output-queuing (OQ) switches have been widely studied, there are few DiffServ scheduling algorithms for input-queuing (IQ) switches in the literaure. In this paper, we propose two algorithms for scheduling DiffServ DiffServ networks with IQ switches: the dynamic DiffServ scheduling (DDS) algorithm and the hierarchical DiffServ scheduling (HDS) algorithm. The basic idea of DDS and HDS is to schedule EF and AF traffic According to Their minimum service rates with the reserved bandwidth …
Preliminary Study On Optimization Of Data Distribution In Resource Sharing Systems, Grzegorz Chmaj, Krzysztof Walkowiak
Preliminary Study On Optimization Of Data Distribution In Resource Sharing Systems, Grzegorz Chmaj, Krzysztof Walkowiak
Electrical & Computer Engineering Faculty Research
Grid structures are increasingly considered as very convergent with peer-to-peer networks. This paper presents a model of network acting both as grid and peer-to-peer network, used for data computation and distribution. Presented PPLC algorithm is a complete solution for both grid and peer-to-peer points of view. Problem formulation is presented, as well as solution heuristic algorithm and research results.
Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj
Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj
Electrical & Computer Engineering Faculty Research
Nesting algorithms deal with placing two dimensional shapes on the given canvas. In this paper a binary way of solving the nesting problem is proposed. Geometric shapes are quantized into binary form, which is used to operate on them. After finishing nesting they are converted back into original geometrical form. Investigations showed, that there is a big influence of quantization accuracy for the nesting effect. However, greater accuracy results with longer time of computation. The proposed knowledge base system is able to strongly reduce the computational time.
Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng
Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng
Electrical & Computer Engineering Faculty Research
Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line …