Computer and Systems Architecture Commons^™

An Experimental Study For Inter-User Interference Mitigation In Wireless Body Sensor Networks, Bin Cao, Yu Ge, Chee Wee Kim, Gang Feng, Hwee-Pink Tan, Yun Li

Research Collection School Of Computing and Information Systems

Inter-user interference degrades the reliability of data delivery in wireless body sensor networks (WBSNs) in dense deployments when multiple users wearing WBSNs are in close proximity to one another. The impact of such interference in realistic WBSN systems is significant but is not well explored. To this end, we investigate and analyze the impact of inter-user interference on packet delivery ratio (PDR) and throughput. We conduct extensive experiments based on the TelosB WBSN platform, considering unslotted carrier sense multiple access (CSMA) with collision avoidance (CA) and slotted CSMA/CA modes in IEEE 802.15.4 MAC, respectively. In order to mitigate interuser interference, …

Clustering Algorithms For Maximizing The Lifetime Of Wireless Sensor Networks With Energy-Harvesting Sensors, Pengfei Zhang, Gaoxi Xiao, Hwee-Pink Tan

Research Collection School Of Computing and Information Systems

Motivated by recent developments in wireless sensor networks (WSNs), we present several efficient clustering algorithms for maximizing the lifetime of WSNs, i.e., the duration till a certain percentage of the nodes die. Specifically, an optimization algorithm is proposed for maximizing the lifetime of a single-cluster network, followed by an extension to handle multi-cluster networks. Then we study the joint problem of prolonging network lifetime by introducing energy-harvesting (EH) nodes. An algorithm is proposed for maximizing the network lifetime where EH nodes serve as dedicated relay nodes for cluster heads (CHs). Theoretical analysis and extensive simulation results show that the proposed …

Evaluating The Presence Of A Victim Cache On An Arm Processor, Lakshmi Vidya Peri

Computer Science Graduate Projects and Theses

Mobile processor is a CPU designed to save power. It is found in mobile computers and cell phones. A CPU chip, designed for portable computers, is typically housed in a smaller chip package, but more importantly, in order to run cooler, it uses lower voltages than its desktop counterpart and has more "sleep mode" capability. A mobile processor can be throttled down to different power levels and/or sections of the chip can be turned off entirely when not in use. ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA). The relative simplicity of ARM processors makes …

High-Performance, Scalable Optical Network-On-Chip Architectures, Xianfang Tan

UNLV Theses, Dissertations, Professional Papers, and Capstones

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with …

Energy-Neutral Scheduling And Forwarding In Environmentally-Powered Wireless Sensor Networks, Alvin Cerdena Valera, Weng Seng Soh, Hwee-Pink Tan

Research Collection School Of Computing and Information Systems

In environmentally-powered wireless sensor networks (EPWSNs), low latency wakeup scheduling and packet forwarding is challenging due to dynamic duty cycling, posing time-varying sleep latencies and necessitating the use of dynamic wakeup schedules. We show that the variance of the intervals between receiving wakeup slots affects the expected sleep latency: when the variance of the intervals is low (high), the expected latency is low (high). We therefore propose a novel scheduling scheme that uses the bit-reversal permutation sequence (BRPS) – a finite integer sequence that positions receiving wakeup slots as evenly as possible to reduce the expected sleep latency. At the …

On High-Performance Parallel Decimal Fixed-Point Multiplier Designs, Ming Zhu

College of Engineering: Graduate Celebration Programs

Decimal computations are required in finance, and etc.

• Precise representation for decimals (E.g. 0.2, 0.7… )
• Performance Requirements (Software simulations are very slow)

Accelerated Data Delivery Architecture, Michael L. Grecol

College of Graduate Studies: Theses & Dissertations

This paper introduces the Accelerated Data Delivery Architecture (ADDA). ADDA establishes a framework to distribute transactional data and control consistency to achieve fast access to data, distributed scalability and non-blocking concurrency control by using a clean declarative interface. It is designed to be used with web-based business applications. This framework uses a combination of traditional Relational Database Management System (RDBMS) combined with a distributed Not Only SQL (NoSQL) database and a browser-based database. It uses a single physical and conceptual database schema designed for a standard RDBMS driven application. The design allows the architect to assign consistency levels to entities …

Cognitive Architectures And Autonomy: Commentary And Response, Włodzisław Duch, Ah-Hwee Tan, Stan Franklin

Research Collection School Of Computing and Information Systems

This paper provides a very useful and promising analysis and comparison of current architectures of autonomous intelligent systems acting in real time and specific contexts, with all their constraints. The chosen issue of Cognitive Architectures and Autonomy is really a challenge for AI current projects and future research. I appreciate and endorse not only that challenge but many specific choices and claims; in particular: (i) that “autonomy” is a key concept for general intelligent systems; (ii) that “a core issue in cognitive architecture is the integration of cognitive processes ....”; (iii) the analysis of features and capabilities missing in current …

Sensor Openflow: Enabling Software-Defined Wireless Sensor Networks, Tie Luo, Hwee-Pink Tan, Tony Q. S. Quek

Research Collection School Of Computing and Information Systems

While it has been a belief for over a decade that wireless sensor networks (WSN) are application-specific, we argue that it can lead to resource underutilization and counter-productivity. We also identify two other main problems with WSN: rigidity to policy changes and difficulty to manage. In this paper, we take a radical, yet backward and peer compatible, approach to tackle these problems inherent to WSN. We propose a Software-Defined WSN architecture and address key technical challenges for its core component, Sensor OpenFlow. This work represents the first effort that synergizes software-defined networking and WSN.

Effects Of Architecture On Information Leakage Of A Hardware Advanced Encryption Standard Implementation, Eric A. Koziel

Theses and Dissertations

Side-channel analysis (SCA) is a threat to many modern cryptosystems. Many countermeasures exist, but are costly to implement and still do not provide complete protection against SCA. A plausible alternative is to design the cryptosystem using architectures that are known to leak little information about the cryptosystem's operations. This research uses several common primitive architectures for the Advanced Encryption Standard (AES) and assesses the susceptibility of the full AES system to side-channel attack for various primitive configurations. A combined encryption/decryption core is also evaluated to determine if variation of high-level architectures affects leakage characteristics. These different configurations are evaluated under …

Cpu Scheduling For Power/Energy Management On Heterogeneous Multicore Processors, Rajesh Patel

UNLV Theses, Dissertations, Professional Papers, and Capstones

Power and energy have become increasingly important concerns in the design and implementation of today's multicore/manycore chips. Many methods have been proposed to reduce a microprocessor's power usage and associated heat dissipation, including scaling a core's operating frequency. However, these techniques do not consider the dynamic performance characteristics of an executing process at runtime, the execution characteristics of the entire task to which this process belongs, the process's priority, the process's cache miss/cache reference ratio, the number of context switches and CPU migrations generated by the process, nor the system load. Also, many of the techniques that employ dynamic frequency …

Ifalcon: A Neural Architecture For Hierarchical Planning, Budhitama Subagdja, Ah-Hwee Tan

Research Collection School Of Computing and Information Systems

Hierarchical planning is an approach of planning by composing and executing hierarchically arranged predefined plans on the fly to solve some problems. This approach commonly relies on a domain expert providing all semantic and structural knowledge. One challenge is how the system deals with incomplete ill-defined knowledge while the solution can be achieved on the fly. Most symbolic-based hierarchical planners have been devised to allow the knowledge to be described expressively. However, in some cases, it is still difficult to produce the appropriate knowledge due to the complexity of the problem domain especially if the missing knowledge must be acquired …

Cuda Web Api Remote Execution Of Cuda Kernels Using Web Services, Massimo J. Becker

Master's Theses

Massively parallel programming is an increasingly growing field with the recent introduction of general purpose GPU computing. Modern graphics processors from NVIDIA and AMD have massively parallel architectures that can be used for such applications as 3D rendering, financial analysis, physics simulations, and biomedical analysis. These massively parallel systems are exposed to programmers through in- terfaces such as NVIDIAs CUDA, OpenCL, and Microsofts C++ AMP. These frame- works expose functionality using primarily either C or C++. In order to use these massively parallel frameworks, programs being implemented must be run on machines equipped with massively parallel hardware. These requirements limit …

A Scalable Inline Cluster Deduplication Framework For Big Data Protection, Yinjin Fu, Hong Jiang, Nong Xiao

School of Computing: Technical Reports

Cluster deduplication has become a widely deployed technology in data protection services for Big Data to satisfy the requirements of service level agreement (SLA). However, it remains a great challenge for cluster deduplica- tion to strike a sensible tradeoff between the conflicting goals of scalable dedu- plication throughput and high duplicate elimination ratio in cluster systems with low-end individual secondary storage nodes. We propose Σ-Dedupe, a scalable inline cluster deduplication framework, as a middleware deployable in cloud da- ta centers, to meet this challenge by exploiting data similarity and locality to op- timize cluster deduplication in inter-node and intra-node scenarios, …

Extreme Learning Machine Terrain-Based Navigation For Unmanned Aerial Vehicles, Ee May Kan, Meng Hiot Lim, Yew Soon Ong, Ah-Hwee Tan, Swee Ping Yeo

Research Collection School Of Computing and Information Systems

Unmanned aerial vehicles (UAVs) rely on global positioning system (GPS) information to ascertain its position for navigation during mission execution. In the absence of GPS information, the capability of a UAV to carry out its intended mission is hindered. In this paper, we learn alternative means for UAVs to derive real-time positional reference information so as to ensure the continuity of the mission. We present extreme learning machine as a mechanism for learning the stored digital elevation information so as to aid UAVs to navigate through terrain without the need for GPS. The proposed algorithm accommodates the need of the …

Erasure Techniques In Mrd Codes, Florentin Smarandache, W.B. Vasantha Kandasamy, R. Sujatha, R.S. Raja Durai

Branch Mathematics and Statistics Faculty and Staff Publications

In this book the authors study the erasure techniques in concatenated Maximum Rank Distance (MRD) codes. The authors for the first time in this book introduce the new notion of concatenation of MRD codes with binary codes, where we take the outer code as the RD code and the binary code as the inner code. The concatenated code consists of the codewords of the outer code expressed in terms of the alphabets of the inner code. These new class of codes are defined as CRM codes. This concatenation techniques helps one to construct any CRM code of desired minimum distance …

Architecture For A Flexible And Scalable Simulation Engine, Robert C. Holcomb Jr.

Computational Modeling & Simulation Engineering Theses & Dissertations

Simulation is used by many different industries to gain insight on actions and decisions that may be too dangerous or costly to perform in reality. Although the use of computers to assist with modeling and simulation has been studied for quite a while, computer infrastructure, hardware, and capabilities are changing at a rapid pace. Computer software once written is difficult and costly to change, especially in order to take advantage of the advances in computer hardware. This thesis focuses on the design and implementation of a software simulation architecture that allows flexibility in the modeling conducted and scalability in the …

A Hybrid Agent Architecture Integrating Desire, Intention And Reinforcement Learning, Ah-Hwee Tan, Yew-Soon Ong, Akejariyawong Tapanuj

Research Collection School Of Computing and Information Systems

This paper presents a hybrid agent architecture that integrates the behaviours of BDI agents, specifically desire and intention, with a neural network based reinforcement learner known as Temporal DifferenceFusion Architecture for Learning and COgNition (TD-FALCON). With the explicit maintenance of goals, the agent performs reinforcement learning with the awareness of its objectives instead of relying on external reinforcement signals. More importantly, the intention module equips the hybrid architecture with deliberative planning capabilities, enabling the agent to purposefully maintain an agenda of actions to perform and reducing the need of constantly sensing the environment. Through reinforcement learning, plans can also be …

Resizable, Scalable, Concurrent Hash Tables Via Relativistic Programming, Josh Triplett, Paul E. Mckenney, Jonathan Walpole

Computer Science Faculty Publications and Presentations

Presentation focusing on software synchronization, thread locking, transactional memory, and relativistic programming. Hash table algorithms are presented with examples of relativistic list insertion and removal, and related data structures. Existing approaches are compared to new methodologies and future work with relativistic data structures.

Resizable, Scalable, Concurrent Hash Tables, Josh Triplett, Paul E. Mckenney, Jonathan Walpole

Computer Science Faculty Publications and Presentations

We present algorithms for shrinking and expanding a hash table while allowing concurrent, wait-free, linearly scalable lookups. These resize algorithms allow the hash table to maintain constant-time performance as the number of entries grows, and reclaim memory as the number of entries decreases, without delaying or disrupting readers.

We implemented our algorithms in the Linux kernel, to test their performance and scalability. Benchmarks show lookup scalability improved 125x over readerwriter locking, and 56% over the current state-of-the-art for Linux, with no performance degradation for lookups during a resize.

To achieve this performance, this hash table implementation uses a new concurrent …

Using Service Responsibility Tables To Supplement Uml In Analyzing E-Service Systems, Xin Tan, Steven Alter, Keng Siau

Research Collection School Of Computing and Information Systems

This paper proposes using Service Responsibility Tables (SRTs) as a tool in analyzing e-service systems. First it discusses difficulties and deficiencies of using formal modeling languages such as UML in analyzing e-service systems. It proposes using SRTs as an informal language and lightweight analytical tool to be used by business professionals in analyzing e-service systems. SRTs are based on a service value chain framework but do not rely on abstract concepts and constructs, and therefore can be used by business professionals to supplement UML. We suggest a set of heuristics for transforming SRTs into two key UML diagrams, thereby illustrating …

A Relativistic Enhancement To Software Transactional Memory, Philip William Howard, Jonathan Walpole

Computer Science Faculty Publications and Presentations

Relativistic Programming is a technique that allows low overhead, linearly-scalable concurrent reads. It also allows joint access parallelism between readers and a writer. Unfortunately, it has so far been limited to a single writer so it does not scale on the write side. Software Transactional Memory (STM) is a technique that allows programs to take advantage of disjoint access parallelism on both the read-side and write-side. Unfortunately, STM systems have a higher overhead than many other synchronization mechanisms so although STM scales, STM starts from a lower baseline. We propose combining relativistic programming and software transactional memory in a way …

Design And Performance Analysis Of Mac Schemes For Wireless Sensor Networks Powered By Ambient Energy Harvesting, Zhi Ang Eu, Hwee-Pink Tan, Winston K. G. Seah

Research Collection School Of Computing and Information Systems

Energy consumption is a perennial issue in the design of wireless sensor networks (WSNs) which typically rely on portable sources like batteries for power. Recent advances in ambient energy harvesting technology have made it a potential and promising alternative source of energy for powering WSNs. By using energy harvesters with supercapacitors, WSNs are able to operate perpetually until hardware failure and in places where batteries are hard or impossible to replace. In this paper, we study the performance of different medium access control (MAC) schemes based on CSMA and polling techniques for WSNs which are solely powered by ambient energy …

A Cost-Benefit Analysis Of A Campus Computing Grid, Preston M. Smith

Purdue Polytechnic Masters Theses

Any major research institution has a substantial number of computer systems on its campus, often in the scale of tens of thousands. Given that a large amount of scientific computing is appropriate for execution in an opportunistic environment, a campus grid is an inexpensive way to build a powerful computational resource. What is missing, though, is a model for making an informed decision on the cost-effectives of a campus grid. In this thesis, the author describes a model for measuring the costs and benefits of building a campus computing resource based on the institution’s existing investment in computing hardware.

For …

Interactivity-Constrained Server Provisioning In Large-Scale Distributed Virtual Environments, Nguyen Binh Duong Ta, Thang Nguyen, Suiping Zhou, Xueyan Tang, Wentong Cai, Rassul Ayani

Research Collection School Of Computing and Information Systems

Maintaining interactivity is one of the key challenges in distributed virtual environments (DVE), e.g., online games, distributed simulations, etc., due to the large, heterogeneous Internet latencies; and the fact that clients in a DVE are usually geographically separated. In this paper, we consider a new problem, termed the interactivity-constrained server provisioning problem, whose goal is to minimize the number of distributed servers needed to achieve a pre-determined level of interactivity. We identify and formulate two variants of this new problem and show that they are both NP-hard via reductions to the set covering problem. We then propose several computationally efficient …

Propeller: A Scalable Metadata Organization For A Versatile Searchable File System, Lei Xu, Hong Jiang, Xue Liu, Lei Tian, Yu Hua, Jian Hu

School of Computing: Technical Reports

The exponentially increasing amount of data in file systems has made it increasingly important for users, administrators and applications to be able to fast retrieve files using file-search services, instead of replying on the standard file system API to traverse the hierarchical namespaces.  The quality of the file-search services  is significantly affected by the file-indexing overhead, the file-search performance and the accuracy of search results.  Unfortunately, the existing file-search solutions either are so poorly scalable that their performance degrades unacceptably when the systems scale up, or incur so much crawling delays that they produce acceptably inaccurate results.  We believe that …

A Multi Agent System For Flow-Based Intrusion Detection Using Reputation And Evolutionary Computation, David Hancock

Theses and Dissertations

The rising sophistication of cyber threats as well as the improvement of physical computer network properties present increasing challenges to contemporary Intrusion Detection (ID) techniques. To respond to these challenges, a multi agent system (MAS) coupled with flow-based ID techniques may effectively complement traditional ID systems. This paper develops: 1) a scalable software architecture for a new, self-organized, multi agent, flow-based ID system; and 2) a network simulation environment suitable for evaluating implementations of this MAS architecture and for other research purposes. Self-organization is achieved via 1) a reputation system that influences agent mobility in the search for effective vantage …

An Architecture For Improving Timeliness And Relevance Of Cyber Incident Notifications, James L. Miller

Theses and Dissertations

This research proposes a communications architecture to deliver timely and relevant cyber incident notifications to dependent mission stakeholders. This architecture, modeled in Unified Modeling Language (UML), eschews the traditional method of pushing notifications via message as dictated in Air Force Instruction 33-138. It instead shifts to a pull or publish and subscribe method of making notifications. Shifting this paradigm improves the notification process by empowering mission owners to identify those resources on which they depend for mission accomplishment, provides a direct conduit between providing and dependent mission owners for notifications when an incident occurs, and provides a shared representation for …

Defensive Cyber Battle Damage Assessment Through Attack Methodology Modeling, Ryan T. Ostler

Theses and Dissertations

Due to the growing sophisticated capabilities of advanced persistent cyber threats, it is necessary to understand and accurately assess cyber attack damage to digital assets. This thesis proposes a Defensive Cyber Battle Damage Assessment (DCBDA) process which utilizes the comprehensive understanding of all possible cyber attack methodologies captured in a Cyber Attack Methodology Exhaustive List (CAMEL). This research proposes CAMEL to provide detailed knowledge of cyber attack actions, methods, capabilities, forensic evidence and evidence collection methods. This product is modeled as an attack tree called the Cyber Attack Methodology Attack Tree (CAMAT). The proposed DCBDA process uses CAMAT to analyze …

Spear Phishing Attack Detection, David T. Merritt

Theses and Dissertations

This thesis addresses the problem of identifying email spear phishing attacks, which are indicative of cyber espionage. Spear phishing consists of targeted emails sent to entice a victim to open a malicious file attachment or click on a malicious link that leads to a compromise of their computer. Current detection methods fail to detect emails of this kind consistently. The SPEar phishing Attack Detection system (SPEAD) is developed to analyze all incoming emails on a network for the presence of spear phishing attacks. SPEAD analyzes the following file types: Windows Portable Executable and Common Object File Format (PE/COFF), Adobe Reader, …