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Air Force Institute of Technology

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Articles 391 - 413 of 413

Full-Text Articles in Computer Engineering

Formal Verification Of Digital Logic, Stuart L. Labovitz Dec 1991

Formal Verification Of Digital Logic, Stuart L. Labovitz

Theses and Dissertations

The most widely used technique for checking the correctness of digital circuits designs is simulation. As the complexity of digital circuits has continued to grow, however, circuit designers have become unable to perform complete simulations of their integrated circuits. Formal hardware verification provides an alternative approach, performing a series of mathematical proofs in order to show that the construction of the circuit from its submodules will result in the intended overall circuit behavior. Papers by Barrow in 1983 and 1984 discuss a PROLOG-based hierarchical formal circuit verification system named VERIFY. AFIT VERIFY, a simple, experimental reverse-engineered version of Barrow's VERIFY …

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Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr. Dec 1991

Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.

Theses and Dissertations

An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements …

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Speech Recognition Using Multiple Features And Multiple Recognizers, Thomas F. Rathbun Dec 1991

Speech Recognition Using Multiple Features And Multiple Recognizers, Thomas F. Rathbun

Theses and Dissertations

The purpose of this thesis is to demonstrate the feasibility of using multiple features and multiple recognizers to perform isolated word recognition. This is accomplished by performing multiple independent recognition tests and fusing the results together to get a single recognition result. The speech data is recorded and each word is extracted into a separate file. Eight features are calculated for each word. The features are calculated on 512 sample time slices and produce 16 component vector output. The three recognizers use the eight features to produce a total of 24 error distance lists. These lists are then fused together …

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Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen Dec 1991

Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen

Theses and Dissertations

Two microcircuits with electrically erasable programmable logic arrays, which use Fowler-Nordheim (F-N) tunneling for both programming and erasing, were designed to demonstrate the use of programmable logic for obsolete TTL logic replacement. Each microcircuit was fabricated in the Orbit 2-micron double-poly low noise analog CMOS process through MOSIS. Software to generate VHDL structural models from a pin list was developed and the logic of both designs was verified by simulation using the Zycad VHDL simulator. The first microcircuit included a simple programmable logic circuit and test cells that allowed measurement of the programming characteristics of the floating gate transistors. Test …

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The Application Of Statistical Estimation Techniques To Terrain Modeling, Donald P. Duckett Jr. Dec 1991

The Application Of Statistical Estimation Techniques To Terrain Modeling, Donald P. Duckett Jr.

Theses and Dissertations

This thesis researches methods of generating accurate and realistic polygonal terrain models by reducing gridded sampled terrain elevation data such as DMA DTED. The terrain models generated should be applicable for use in flight simulators and other systems. Existing methods of terrain modeling are discussed, and limitations of these systems are presented. The geostatistical estimation technique known as kriging is presented as a method estimating terrain elevations at locations not provided in DMA DTED or other gridded terrain elevation data. Kriging is an optimal interpolation method based on statistical analysis of the data. It also provides a measure of accuracy, …

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Implementation Of An Object-Oriented Flight Simulator D.C. Electrical System On A Hypercube Architecture, Guy R. Booth Dec 1991

Implementation Of An Object-Oriented Flight Simulator D.C. Electrical System On A Hypercube Architecture, Guy R. Booth

Theses and Dissertations

The Software Engineering Institute developed an Object-Oriented Paradigm for Flight Simulators based on the concept of mapping the behavior of physical objects from an aircraft into an object-oriented software architecture. This mapping is a semi-formal method that maps objects to a hierarchy that has three logical layers: objects, systems, and executives. The paradigm was developed with the idea of implementing the derived simulation design on a parallel or distributed computer architecture, but no explicity design features are provided for implementing the design on a parallel computer. This research addresses the issue of determining what extensions (if any) are required to …

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Logic Programming In Digital Circuit Design, Joseph W. Eicher Dec 1991

Logic Programming In Digital Circuit Design, Joseph W. Eicher

Theses and Dissertations

The design of large, complex digital circuitry requires highly skilled engineers. Much of the time spent by these engineers in the design phase involves tasks that are repetitive, tedious, and slow. If these repetitive tasks are automated, the engineer can spend more time managing the design process and produce a better-quality design in less time. Logic programming can be used to automate design tasks, even those that require a high degree of skill. This thesis investigates several aspects of the digital circuit design process that involve pattern-matching paradigms suitable for encoding in the logic programming language Prolog.

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Frequency Domain Speech Coding, Shane Switzer Dec 1991

Frequency Domain Speech Coding, Shane Switzer

Theses and Dissertations

The major goal of this research was to investigate speech coding techniques in an attempt to achieve high quality speech transmittable at 4800 bits per second. The approach taken to achieve this goal was to code the frequency domain representation of speech. Speech was represented by a sparse set of frequency components. Four frequency selections schemes were implemented, and the resulting frequency coefficients (magnitude and phase) were coded in an efficient manner for transmission. Specific techniques involved in the speech coder included: (1) a recurrent neural architecture to make a periodic/noiselike decision, (2) the use of variable length windows for …

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Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau Dec 1991

Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau

Theses and Dissertations

VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …

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A Prolog System For Converting Vhdl-Based Models To Generalized Extraction System (Ges) Rules, Michael A. Dukes, Frank M. Brown, Joanne E. Degroat Jun 1991

A Prolog System For Converting Vhdl-Based Models To Generalized Extraction System (Ges) Rules, Michael A. Dukes, Frank M. Brown, Joanne E. Degroat

AFIT Documents

With the advent of VHDL accurate documentation of hardware designs is a practical reality. In the past, schematics were typically used for documentation of hardware designs. However, these schematics would usually become obsolete as the hardware design was being constructed. Deviations in the hardware design would sometimes not be reflected in the schematics. For design groups, failure to update schematics could lead to different parts of a hardware design becoming incompatible. A system to ensure compliance of hardware with its VHDL documentation is presented in this paper. The system, vhdl2ges, is meant to help guide the development of hardware by …

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Hybrid Wafer Scale Microcircuit Integration -- [ 5008213 ], Edward S. Kolesar Jr. Apr 1991

Hybrid Wafer Scale Microcircuit Integration -- [ 5008213 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …

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A Common Interface Real-Time Multiprocessor Operating System For Embedded Systems, Michael S. Rottman Mar 1991

A Common Interface Real-Time Multiprocessor Operating System For Embedded Systems, Michael S. Rottman

Theses and Dissertations

Large real time applications such as aerospace avionics systems, battle management, and factory automation place many demands and constraints on the computing system not found in other applications. Software development is hindered by software dependence on the computer architecture and the lack of portability between systems. This thesis specifies and designs a real time multiprocessor operating system (RTMOS) that implements a consistent programming model, enabling the development of real time parallel software independent of the target architecture. The RTMOS defines the core functionality required to demonstrate the programming model. The RTMOS functional requirements are specified using Structured Analysis and Design …

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A Prolog-Based System For Hardware Verification, Kevin L. Sparks Mar 1991

A Prolog-Based System For Hardware Verification, Kevin L. Sparks

Theses and Dissertations

With the expanding number of components provided on a single digital chip, verification of digital designs is becoming a major problem. The more circuits one places on a single chip, the greater the number of input/output combinations which need to be checked. A paper by Barrow in 1984 discusses a Prolog-based hierarchical formal verification system which he calls VERIFY. Barrow provided a lot of information on what VERIFY can and cannot do, and on projected enhancements. He does not, however, mention how VERIFY actually performs the task of formal verification. This thesis will provide a description of one possible implementation …

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Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor Mar 1991

Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor

Theses and Dissertations

The ultimate purpose of this research is to reduce the time needed for execution of parallel computer simulations. In particular, the impact of task assignment strategies is determined for parallel VHDL circuit simulations. The classical scheduling problem, which assigns n precedence-constrained tasks to m processors is NP-complete in all but the simplest cases. The problem of assigning simulation tasks is further complicated by the iterative nature of computer simulations: each task is required to execute multiple times as the simulation executes. This investigation develops a polynomial-time algorithm (the level strategy) which provides optimal assignment for iterative systems with specific constraints. …

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Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr. Jan 1991

Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …

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Graphical Representation Of Parallel Algorithmic Processes, Edward M. Williams Dec 1990

Graphical Representation Of Parallel Algorithmic Processes, Edward M. Williams

Theses and Dissertations

Algorithm animation is a visualization method used to enhance understanding of functioning of an algorithm or program. Visualization is used for many purposes, including education, algorithm research, performance analysis, and program debugging. This research applies algorithm animation techniques to programs developed for parallel architectures, with specific on the Intel iPSC/2 hypercube. While both P-time and NP-time algorithms can potentially benefit from using visualization techniques, the set of NP-complete problems provides fertile ground for developing parallel applications, since the combinatoric nature of the problems makes finding the optimum solution impractical. The primary goals for this visualization system are: Data should be …

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Sql/Nf Translator For The Triton Nested Relational Database System, Craig W. Schnepf Dec 1990

Sql/Nf Translator For The Triton Nested Relational Database System, Craig W. Schnepf

Theses and Dissertations

The problem addressed in this thesis concerns the design and implementation of a high level data base query language translator based on the nested relational data model. The objective of the model is to increase the performance of the relational model by modeling real-world objects in the problem domain into nested relations. The translator is designed within the EXODUS extensible architectural framework for building application-specific database systems. The SQL/NF query language used for the nested relational model is an extension of the popular relational model query language SQL. The query language is translated into a nested relational algebra (Colby algebra) …

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Extraction And Measurement Of Multi-Level Parallelism In Productions Systems, George A. Sawyer Dec 1990

Extraction And Measurement Of Multi-Level Parallelism In Productions Systems, George A. Sawyer

Theses and Dissertations

Productions systems provide a flexible and powerful means for expressing and solving problems using high-level reasoning approaches. Unfortunately applications based on the production system paradigm are very compute intensive and therefore execute very slowly on conventional computer architectures. Lack of execution speed therefore limits the use of production systems in many time sensitive and complex tasks. Researchers have demonstrated that increasing the execution speed of production systems through the use of small scale parallel computer architecture is possible, however demonstrated execution speed is still several orders of magnitude below the desired level of performance. Past research indicates that there exists …

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A Low-Cost Part-Task Flight Training System: An Application Of A Head Mounted Display, David A. Dahn Dec 1990

A Low-Cost Part-Task Flight Training System: An Application Of A Head Mounted Display, David A. Dahn

Theses and Dissertations

To investigate the feasibility of using head-mounted display(HMD) and Computer Image Generators(CIG) in a low cost part-task trainer, we created a prototype system. Our approach was to build a virtual world interface using a HMD to an existing flight simulator application. This allowed a CIG with only one graphics channel to drive the display. To investigate which class of computing platform was suitable for use as the CIG, a cooperative thesis effort was launched to host the simulator on a mini-computer and micro-computer platform. The appropriate CIG could then be determined through demonstration and comparison between the systems. A software …

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Multi-Input Multi-Output Flight Control System Design For The Yf-16 Using Nonlinear Qft And Pilot Compensation, Russell B. Miller Dec 1990

Multi-Input Multi-Output Flight Control System Design For The Yf-16 Using Nonlinear Qft And Pilot Compensation, Russell B. Miller

Theses and Dissertations

Nonlinear Quantitative Feedback Theory (QFT) and pilot compensation techniques are used to design a 2x2 flight control system for the YF-16 aircraft over a large range of plant uncertainty. The design is based on numerical input- output time histories generated with a FORTRAN implemented nonlinear simulation of the YF-16. The first step of the design process is the generation of a set of equivalent linear time-invariant (LTI) plant models to represent the actual nonlinear plant. It has been proven that the solution to the equivalent plant problem is guaranteed to solve the original nonlinear problem. Standard QFT techniques are then …

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Recursive Optimization Of Digital Circuits, John Knutson Dec 1990

Recursive Optimization Of Digital Circuits, John Knutson

Theses and Dissertations

The goal of this thesis is twofold: first, to identify the advantages and disadvantages of existing optimization systems and second, to develop an optimization system that uses Boolean principles to generate a recursive realization of combinational logic. Current multi-level optimization systems fall into two categories: local optimization which removes redundancy by pattern matching on a local scale and global optimization which works with the equations that specify a circuit rather than with the circuit implementation itself. While global systems are very flexible and can produce near-optimal solutions, they are inherently complex. This research effort demonstrates that an effective global optimization …

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Specification And Equivalence Verification Of Sequential Circuits Via Vhdl, Richard L. Miller Nov 1990

Specification And Equivalence Verification Of Sequential Circuits Via Vhdl, Richard L. Miller

Theses and Dissertations

This research presents a merger of the specification and design capabilities of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) with a known verification method (UC Berkeley's verify software) in order to solve the design and verification problem of sequential circuits. The fruits of this research are a behavioral VHDL model for sequential circuit specification, a structural VHDL model for sequential circuit design, and a method for comparing two circuits described using these VHDL models in order to demonstrate circuit equivalence. The behavioral and structural VHDL models were developed and tested within the Intermetric's VHDL software support …

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Software Simulation Of The D17b Computer, Bruce Chatterton Mar 1972

Software Simulation Of The D17b Computer, Bruce Chatterton

Theses and Dissertations

A software program has been written which simulates the functions of the Minuteman D17B computer at the register transfer level. The simulation program is written in the FORTRAN Extended language to be used on the Intercom System (teletype) of a CDC 6600 computer system. The simulation program consists of a main program and eight subroutines. A programming language for the D17B simulation was formed which contains numbers and load codes, switches, and miscellaneous commands. Example programs run on the simulated computer have been included to show the types of output available.

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