Computer Engineering Commons^™

Congruent Weak Conformance, Ronald W. Brower

Theses and Dissertations

This research addresses the problem of verifying implementations against specifications through an innovative logic approach. Congruent weak conformance, a formal relationship between agents and specifications, has been developed and proven to be a congruent partial order. This property arises from a set of relations called weak conformations. The largest, called weak conformance, is analogous to Milner's observational equivalence. Weak conformance is not an equivalence, however, but rather an ordering relation among processes. Weak conformance allows behaviors in the implementation that are unreachable in the specification. Furthermore, it exploits output concurrencies and allows interleaving of extraneous output actions in the implementation. …

Rekabentuk Perkakasan Khas Ecc (Reed-Solomon), Muhamad Mursid Noorizan

Student Works (2000-2009)

Dokumen ini disiapknn bagi menyediakan laporan tentang perjalanan projek perkakasan khas ECC yang dijalankan. Bahagian pertama dokumen ini terdapat pengenalan tentang projek. Bahagian kedua pula menyatakan tentang kajian yang telah dilakukan bagi memilih kod-kod pembetulan yang ingin dibangunkan. Seterusnya pada bahagian tiga, dinyatakan serba sedikit tentang bahasa yang digunakan dalam pembangunan projek iaitu VHDL. Sahagian keempat pula menceritakan tentang senibina-senibina dan rekabentuk-rekabentuk perkakasan khas. Dalam bahagian lima, dokumen menceritakan tentang fasa pembangunan yang telah dijalankan. Bahagian enam dan tujuh pula menceritakan tentang perbincangan dan kesimpulan daripada projek yang telah dijalankan.

Keyboard - Smart Card Reader Controller Using Vhdl, Lani Mohd Zuwairi

Student Works (2000-2009)

As the time fly by the technology of computers has improves and much security is needed in every transaction of data that being done. In this project, designing a microcontroller for keyboard and smart card reader terminal integration is being done. At first stage, the architecture of the controller will analyze and studied. This will need some practice of knowledge in computer organization and architecture, as well as microprocessors architecture designs. Then the architecture is design using hardware prototyping. This is by using the VHSIC Hardware Description Language (VHDL). The codes done using the language then being simulate to get …

Studies Related To The Design And Implementation Of A Magnetic Suspension And Balance System, Syed Adeel Akhtar Jafri

Electrical & Computer Engineering Theses & Dissertations

This thesis presents studies related to the magnetic suspension and balance system (MSBS) of the Princeton/ONR High Reynolds Number Testing Facility (HRTF). The main motivation for developing the MSBS is to provide interference free aero/hydrodynamic testing of submersible models, which will lead to more accurate measurements. From the controls point of view, the main specification of the MSBS is to robustly control the position of a submersible model in five degrees of freedom (DOF), including three translational as well as pitching and yawing positions. The MSBS should not only regulate the submersible model's position but should also allow for small …

Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor

Student Works (2000-2009)

Tesis ini menghuraikan sebuah pendarab titik apungan 32bit bertalian paip 18MHz yang direkabentuk menggunakan bahasa perihalan perkakasan YHDL, peralatan sintesis Synopsys FPGA Express dan ·peralatan pemetaan Xilinx Alliance, PTA ini menggunakan 1007 CLB dan 100 10B di mana peranti pemetaan yang digunakan ialah xc4036xl-bg432-2 daripada pustaka XC4000 Xilinx FPGA. Pendarab ini mengandungi tiga tahap talian paip yang belainan fungsi. Tahap pertama melaksanakan penjanaan dedarab dan penambahan dedarab secara carry save dan penambahan eksponen. la menggunakan algoritma Booth tertib kedua dan pepohon Wallace dengan pemampat 4-2. Tahap kcdua pula melakukan penambahan bawaan rambatan akhir, penormalan mantisa dan pembetulan eksponen manakala tahap …

Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani

Student Works (2000-2009)

ALU testing mechanism using Boundary Scan technique is a project which is develop to be the tester for testing the digital circuit, integrated circuit and computer chip. The goal of this project is to develop a mechanism and as well building an ALU chip so that we will able to test and determine whether the chips are in a good shape and condition. This project contains two parts: one is lo develop an ALU and second is to develop the boundary scan chip. ALU is a unit or a component for a cligital circuit or a integrated circuit which is …

Rekabentuk Cip Pemamtapatan Data, Ismail Shah Rizal

Student Works (2000-2009)

Dokumen ini telah disiapkan untuk membuat cadangan projek Timiah Tahun Akhir yang bertajuk Rekabentuk Perkakasan Cip Pemampatan Data. Babagian pertama adalah berkenaan pengenalan yang memberi gambaran tentang tujuan, objektif dan kepenringan projek juga keperluan perkakasan dan perisian dalarn proses pembanguoan. Bahagian kedua pula, tumpuan diberikan kepada pemampatan data iaitu jenis teknik, algoritma Huffman dan contoh penggunaan Huffman. Dalarn bahagian ketiga, pengenalan terhadap perisian yang akan digunakan iaitu perisian VHDL. Bahagian keempat dokumen menyentuh tentang pendekatan pembangunan modul rekabentuk dan rekabentuk akhir perkakasan yang akan dibangunkan. Juga turut dimasukkan ialab gambarajah status bertujuan untuk memudahkan pemahaman. Dalam bahagian lima pula, implementasi …

Digital Receivers, George Rofa

Theses : Honours

No abstract provided.

Remotely Possible? Simple Remote Access To The Network, Margaret Sylvia

Faculty Publications

Remote access to the library is possible without a magic wand. we have seen increased use of the library in recent years, either because of, or despite, the possibility of remote access. One reason may be that some full-text material is still only available inside the library. Remote access was first implemented in the St. Mary's University Academic Library in 1991, shortly after the installation of the first network in the library. Various options for remote access are compared and contrasted, including the EA/2 solution.

Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain

Computer Science and Engineering Research

An important stage in circuit design is placement, where components are assigned to physical locations on a chip. A popular contemporary approach for placement is the use of simulated annealing. While this approach has been shown to produce good placement solutions, recent work in genetic algorithms has produced promising results. The purpose of this study is to determine which approach will result in better placement solutions.

A simplified model of the placement problem, circuit partitioning, was tested on three circuits with both a genetic algorithm and a simulated annealing algorithm. When compared with simulated annealing, the genetic algorithm was found …

Speech Feature Computation For Visual Speech Articulation Training, Stefan Auberg

Electrical & Computer Engineering Theses & Dissertations

A new version of the Visual Speech Articulation Training Aid was implemented which provides real-time visual feedback for speech articulation training. This version was migrated to a Windows Multimedia PC from a previous version which used a Personal Computer (PC) system and additional specialized and expensive custom hardware. This new version will make the system more available to schools and private users. A new method was developed for computing spectral/temporal features which characterize the speech sounds. In addition to the typical frame-based spectral analysis parameters, the new method represents temporal changes of the spectrum with a small number of features. …

Upgrading A Cd-Rom Network For Multimedia Applications, Margaret Sylvia

Faculty Publications

Checking the servers, PCs, and network connections for bottlenecks in serving multimedia across the network are steps that will alleviate speed and connectivity issues for users.

Ua3/8/5 Wku Network Campus Map, Wku President's Office-Meredith

WKU Administration Documents

Map of WKU campus computer networking project.

Rapid And Accurate Timing Simulation Of Radiation-Hardened Digital Microelectronics Using Vhdl, Charles P. Brothers Jr.

Theses and Dissertations

This dissertation presents the development of a fast, accurate, timing simulation capability based on VHSIC Hardware Description Language VHDL without the use of back annotation of timing delay information. This VHDL-based timing simulator is intended for use with radiation-hardened microelectronics in simulating timing of circuit operation in pre-radiation, post-radiation 1 MradSi total dose, and ionizing dose radiation environments. Development of the timing models are presented. The implementation of the timing models are incorporated into a VHDL library composed of basic logic gates and flip-flops. Simulations of complex circuits were run in SPICE and VHDL to assess the timing accuracy and …

Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp

Theses and Dissertations

Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …

Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead

Theses and Dissertations

Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts …

Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin

Theses and Dissertations

A Parallel Discrete Event Simulation Coprocessor was designed to off- load the synchronization overhead from the processors executing the application. In a multiprocessor architecture, one coprocessor executes the synchronization routines for each host processor. Speedup can be achieved when the host processor executes the application and the coprocessor concurrently executes synchronization routines. The coprocessor uses a programmable microcode control store to guarantee flexibility in the synchronization routines. The coprocessor uses an Extreme Search Associative Memory to support fast Next Event Queue NEQ management. This associative memory uses bit-serial word-parallel search logic to provide 01 insert and retrieval time of events …

Networking Your Cd-Roms: A Texas Tale, Margaret Sylvia

Faculty Publications

Installation of a CD-ROM network at St. Mary's University Academic Library created a revolution in the way students and faculty do research.

A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton

Theses and Dissertations

The dissertation develops a decision criteria to select an associative-memory organization that minimizes the execution time of a mix of associative-search operations and a decision criteria to estimate the layout dimensions of each organization for a specified memory size. The dissertation reclassifies Feng's associative-search operations into three hardware-influenced categories: bit-position independent (BPI), record-content independent (RCI); bit-position dependent (BPD), RCI; and BPD, record-content dependent (RCD). It develops a relationship between the categories and three associative-memory organizations: the CAM, the bit-serial word-parallel associative memory (BSWPAM) , and the extreme-search associative memory (ESAM). A version of the CAM, three versions of the BSWPAM, …

Building A Gateway For The Cd-Rom Network: A Step Toward The Virtual Library With The Virtual Microsystems V-Server, Margaret Sylvia

Faculty Publications

Describes one college library's experience with a gateway for dial-in access to its CD-ROM network to increase access to automated index searching for students off-campus. Hardware and software choices are discussed in terms of access, reliability, affordability, and ease of use. Installation problems are discussed, and an appendix lists product information.

A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh

Computer Science: Faculty Publications and Other Works

This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.

Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel

Theses and Dissertations

A hardware discrete event simulation (DES) coprocessor was designed to eliminate synchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design …

Design And Implementation Of Fuzzy Logic Controllers. Thesis Final Report, 27 July 1992 - 1 January 1993, Osama A. Abihana, Oscar R. Gonzalez

Electrical & Computer Engineering Faculty Publications

The main objectives of our research are to present a self-contained overview of fuzzy sets and fuzzy logic, develop a methodology for control system design using fuzzy logic controllers, and to design and implement a fuzzy logic controller for a real system. We first present the fundamental concepts of fuzzy sets and fuzzy logic. Fuzzy sets and basic fuzzy operations are defined. In addition, for control systems, it is important to understand the concepts of linguistic values, term sets, fuzzy rule base, inference methods, and defuzzification methods. Second, we introduce a four-step fuzzy logic control system design procedure. The design …

A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin

Theses and Dissertations

Model-based reasoning permits diagnostic applications to be written without waiting for someone to become an 'expert' of the system. For model-based diagnostics, there must be a model to reason from. This thesis explores using a VHDL description of the system as that model. A system based around a VHDL interpreter was written specifically for a model-based diagnostic algorithm. Currently, the diagnostic system uses an algorithm by Dries. This algorithm was derived from Scarl's Full Consistency Algorithm. The system was designed to be modular so that different diagnostic techniques could be implemented. It is divided into three parts: a VHDL parser, …

Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young

Theses and Dissertations

We develop a methodology for formalizing, verifying, and validating the requirements specification of real-time systems based on a graphical and formal hierarchical Finite State Machine (FSM) language Reacto. We define a means to quantify time and express real-time constraints in Reacto and a transformation from Reacto to the Very High Speed Integrated Circuit (VHSIC) hardware Description Language (VHDL). Reacto's high level abstractions, graphical nature, and theorem prover produce efficient, accurate, and easily understood specifications. We use VHDL's event driven simulation capability, concurrency, and temporal operators to thoroughly examine temporal dependencies between the state machine transitions, and to increase simulation power …

Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.

Theses and Dissertations

An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements …

Simulator For Concurrent Processing Data Flow Architectures, Mahyar R. Malekpour

Electrical & Computer Engineering Theses & Dissertations

A software simulator capable of simulating execution of an algorithm graph on a given system under the Algorithm To Architecture Mapping Model (ATAMM) rules is presented in this thesis. ATAMM is capable of modeling the execution of large-grained algorithms on distributed data flow architectures. Investigating the behavior and determining the performance of an ATAMM based system requires the aid of software tools. The ATAMM Simulator presented in this thesis is capable of determining the behavior, performance, and reliability of a system without having to build a hardware prototype. Case studies are performed on four algorithms to demonstrate the capabilities of …

Computerised Selection Of Materials And Reliability, Nabil Ibrahim Mikhail

Archived Theses and Dissertations

No abstract provided.

An Inventory Of Maine's Telecommunications System, Maine State Planning Office

Maine Collection

An Inventory of Maine's Telecommunications System

Prepared for the Maine State Planning Office by Joseph M. Chaisson and Valerie Lamont of the Telecommunications Research Program at Westbrook College in Portland, Maine. July, 1985.

"The Primary purpose of this report is to provide information for Governor Brennan's Task Force on Telecommunications. The inventory also can be widely used as a reference by persons and organizations concerned with providing telecommunications services in Maine."

Contents: Introduction / Local Telephone Service / Mobile Telephone Service / Digital Termination Service / Cable Television / Paging Systems / Intra-State (Intra-LATA) Public Services / Intra-State (Intra-LATA) Private …

Analog Computer Simulation With Automatic Scaling By Digital Computer, Mark Anthony Motter

Electrical & Computer Engineering Theses & Dissertations

A computer-aided design approach for the simplification of analog computer simulation is presented. The simulation configuration consists of an EAI 2000 analog computer with serial communications link to a PDP — 11/24 digital computer. Under control of the PDP-11, the analog simulations are realized with appropriate time and magnitude scaling which adjusts the range of the simulation coefficients and prevents overloads of the analog components. The analog computer hardware configuration accommodates both stable plants up to eighth order and closed-loop systems up to tenth order. Cascade compensation is provided for the closed-loop systems.

The plant may be described by either …