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Full-Text Articles in Computer Engineering

A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin Dec 1992

A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin

Theses and Dissertations

Model-based reasoning permits diagnostic applications to be written without waiting for someone to become an 'expert' of the system. For model-based diagnostics, there must be a model to reason from. This thesis explores using a VHDL description of the system as that model. A system based around a VHDL interpreter was written specifically for a model-based diagnostic algorithm. Currently, the diagnostic system uses an algorithm by Dries. This algorithm was derived from Scarl's Full Consistency Algorithm. The system was designed to be modular so that different diagnostic techniques could be implemented. It is divided into three parts: a VHDL parser, …


Solution To A Multicriteria Aircraft Routing Problem Utilizing Parallel Search Techniques, James J. Grimm Iii Dec 1992

Solution To A Multicriteria Aircraft Routing Problem Utilizing Parallel Search Techniques, James J. Grimm Iii

Theses and Dissertations

Pilots select routes based on factors such as threats, fuel, time on target, distance, and refueling points. This is a time consuming task. This thesis presents the software engineering synthesis of a software tool, based on a parallelized A* search algorithm, to select routes. For simplicity only threats and distance are used. A centralized open list is used with one processor managing the list while the other processors perform the node expansions. This decomposition result in a dynamically load balanced system. A number of parameters are changed to study their impact on the execution time. The use of a branch …


Creating And Manipulating Formalized Software Architectures To Support A Domain-Oriented Application Composition System, Cynthia G. Anderson Dec 1992

Creating And Manipulating Formalized Software Architectures To Support A Domain-Oriented Application Composition System, Cynthia G. Anderson

Theses and Dissertations

This research investigated technology which enables sophisticated users to specify, generate, and maintain application software in domain-oriented terms. To realize this new technology, a development environment, called Architect, was designed and implemented. Using canonical formal specifications of domain objects, Architect rapidly composes these specifications into a software application and executes a prototype of that application as a means to demonstrate its correctness before any programming language specific code is generated. Architect depends upon the existence of a formal object base (or domain model) which was investigated by another student in related research. The research described in this thesis relied on …


An Intelligent Real-Time System Architecture Implemented In Ada, Michael A. Whelan Dec 1992

An Intelligent Real-Time System Architecture Implemented In Ada, Michael A. Whelan

Theses and Dissertations

Conventional real-time systems are fully deterministic allowing for off-line, optimal, task scheduling under all circumstances. Real-time intelligent systems add non-deterministic task execution times and non- deterministic task sets for scheduling purposes. Non-deterministic task sets force intelligent real-time systems to trade-off execution time with solution quality during run-time and perform dynamic task scheduling. Four basic design considerations addressing those tradeoffs have been identified: control reasoning, focus of attention, parallelism, and algorithm efficacy. Non-real- time intelligent systems contain an environment sensor, a model of the environment, a reasoning process, and a large collection of procedural processes. Real-time intelligent systems add to these …


Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young Dec 1992

Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young

Theses and Dissertations

We develop a methodology for formalizing, verifying, and validating the requirements specification of real-time systems based on a graphical and formal hierarchical Finite State Machine (FSM) language Reacto. We define a means to quantify time and express real-time constraints in Reacto and a transformation from Reacto to the Very High Speed Integrated Circuit (VHSIC) hardware Description Language (VHDL). Reacto's high level abstractions, graphical nature, and theorem prover produce efficient, accurate, and easily understood specifications. We use VHDL's event driven simulation capability, concurrency, and temporal operators to thoroughly examine temporal dependencies between the state machine transitions, and to increase simulation power …


Exact Dominance Without Search In Decision Trees, Nilesh L. Jain, Ronald P. Loui Dec 1992

Exact Dominance Without Search In Decision Trees, Nilesh L. Jain, Ronald P. Loui

All Computer Science and Engineering Research

In order to improve understanding of how planning and decision analysis relate, we propose a hybrid model containing concepts from both. This model is comparable to [Hartman90], with slightly more detail. Dominance is simple concept in decision theory. In a restricted version of our model, we give conditions under which dominance can be detected without search: that is, it can be used as a pruning strategy to avoid growing large trees. This investigation follows the lead of [Wellman87]. The conditions seem hard to meet, but may nevertheless be useful in forward-chaining situations without focus, such as [Breese87]. It may be …


Efficient Accommodation Of May-Alias Information In Ssa Form, Ron Cytron, Reid Gershbein Dec 1992

Efficient Accommodation Of May-Alias Information In Ssa Form, Ron Cytron, Reid Gershbein

All Computer Science and Engineering Research

We present an algorithm for incrementally including may-alias information into Static Single Assignment form by computing a sequence of increasingly precise (and correspondingly larger) partial SSA forms. Our experiments show significant speedup of our method over exhaustive use of may-alias information, as optimization problems converge well before most may-aliases are needed.


Generalization And Parallelization Of Messy Genetic Algorithms And Communication In Parallel Genetic Algorithms, Laurence D. Merkle Dec 1992

Generalization And Parallelization Of Messy Genetic Algorithms And Communication In Parallel Genetic Algorithms, Laurence D. Merkle

Theses and Dissertations

Genetic algorithms (GA) are highly parallelizable, robust semi- optimization algorithms of polynomial complexity. The most commonly implemented GAs are 'simple' GAs (SGAs). Reproduction, crossover, and mutation operate on solution populations. Deceptive and GA-hard problems are provably difficult for simple GAs. Messy GAs (MGA) are designed to overcome these limitations. The MGA is generalized to solve permutation type optimization problems. Its performance is compared to another MGA's, an SGA's, and a permutation SGA's. Against a fully deceptive problem the generalized MGA (GMGA) consistently performs better than the simple GA. Against an NP-complete permutation problem, the GMGA performs better than the other …


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 8, November 1992, College Of Engineering And Computer Science, Wright State University Nov 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 8, November 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A fourteen page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


The Programmers' Playground: I/O Abstraction For Heterogeneous Distributed Systems, Kenneth J. Goldman, Michael D. Anderson Nov 1992

The Programmers' Playground: I/O Abstraction For Heterogeneous Distributed Systems, Kenneth J. Goldman, Michael D. Anderson

All Computer Science and Engineering Research

A new high-level approach to interprocess communication in heterogeneous distributed systems in introduced, This approach, called I/O Abstraction, allows one to write each functional component of a distributed system as an encapsulated program that acts upon a set of local data structures, some of which may be published for external use. The functional components are separately configured by establishing logical connections among the published data structures. In order to illustrate this approach, we describe the The Programmers' Playground, a high-level language "veneer" and protocol designed to support I/O abstraction in heterogeneous computing environment. Support for communication among programs written in …


Computing Specificity, Ronald Loui, J. Norman, K. Stiefvater, A. Merrill, A. Costello, J. Olson Nov 1992

Computing Specificity, Ronald Loui, J. Norman, K. Stiefvater, A. Merrill, A. Costello, J. Olson

All Computer Science and Engineering Research

This note reports on an effort to implement a version of Poole's rule for specificity. Relatively, efficient implementation relies on correcting and improving a pruning lemma of Simari-Loui [92]. This in turn requires revision of Poole's specificity concept. The resulting system is a usable knowledge representation system with first-order-language and defeasible reasoning. Sample input and output are included in an appendix. It is a good candidate for multiple inheritance applications; it is useful for planning, but limited by the underlying search for plans.


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 7, October 1992, College Of Engineering And Computer Science, Wright State University Oct 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 7, October 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A ten page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Process And Policy: Resource-Bounded Non-Demonstrative Reasoning, Ronald P. Loui Oct 1992

Process And Policy: Resource-Bounded Non-Demonstrative Reasoning, Ronald P. Loui

All Computer Science and Engineering Research

This paper investigates the appropriateness of formal dialectics as a basis for non-monotonic and defeasible reasoning that takes computational limits seriously. Rules that can come into conflict should be regarded as policies, which are inputs to deliberative processes. Dialectical protocols are appropriate for such deliberations when resources are bounded and search is serial. AI, it is claimed here, is now perfectly positioned to correct many misconceptions about reasoning that have resulted from mathematical logic's enormous success in this century: among them (1) that all reasons are demonstrative, (2) that rational belief is constrained, not constructed, (3) that process and disputation …


Packet Routing In Networks With Long Wires, Ronald I. Greenberg, H.-C. Oh Oct 1992

Packet Routing In Networks With Long Wires, Ronald I. Greenberg, H.-C. Oh

Computer Science: Faculty Publications and Other Works

In this paper, we examine the packet routing problem for networks with wires of differing length. We consider this problem in a network independent context, in which routing time is expressed in terms of “congestion” and “dilation” measures for a set of packet paths. We give, for any constant ε > 0, a randomized on-line algorithm for routing any set of N packets in O((Clg^ε(Nd)+Dlg(Nd))/lglg(Nd)) time, where C is the maximum congestion and D is the length of the longest path, both taking wire delays into account, and d is the longest path in terms of number of wires. We also …


Separating Structure From Function In The Specification And Design Of Distributed Systems, Kenneth J. Goldman Sep 1992

Separating Structure From Function In The Specification And Design Of Distributed Systems, Kenneth J. Goldman

All Computer Science and Engineering Research

A distributed system is viewed as a collection of functional components and a unifying structure that defines relationships among the components. In the paper, we advocate a particular approach to distributed system specification and design in which the structure of a distributed system is specified separately from the functional components. This permits one to reason about individual functional components in isolation, and encourages one to make explicit not only the input/output behavior of the functional components but also the logical placement of these components within the overall structure of the system. We describe a new software tool for the specification, …


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 6, September 1992, College Of Engineering And Computer Science, Wright State University Sep 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 6, September 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Dna Mapping Algorithms: Strategies For Single Restriction Enzyme And Multiple Restriction Enzyme Mapping, Will Gillett Aug 1992

Dna Mapping Algorithms: Strategies For Single Restriction Enzyme And Multiple Restriction Enzyme Mapping, Will Gillett

All Computer Science and Engineering Research

An approach to high-resolution restriction-fragment DNA mapping, known as Multiple-Restriction-Enzyme mapping (MRE mapping), is present. This approach significantly reduces the uncertainty of clone placement by using clone ends to synchronize the position in of clones within different maps, each map being constructed from fragment-length data produced by digestion of each clone with a specific restriction enzyme. Maps containing both fragments-length data and clone-end data are maintained for each restriction enzyme, and synchronization between two such maps is achieved by requiring them to have "compatible" clone-end map projections. Basic definitions of different kinds of maps, such as restriction sites maps, restriction …


Can Pac Learning Algorithms Tolerate Random Attribute Noise?, Sally A. Goldman, Robert H. Sloane Jul 1992

Can Pac Learning Algorithms Tolerate Random Attribute Noise?, Sally A. Goldman, Robert H. Sloane

All Computer Science and Engineering Research

This paper studies the robustness of pac learning algorithms when the instances space is {0,1}n, and the examples are corrupted by purely random noise affecting only the instances (and not the labels). In the past, conflicting results on this subject have been obtained -- the "best agreement" rule can only tolerate small amounts of noise, yet in some cases large amounts of noise can be tolerated. We show that the truth lies somewhere in between these two alternatives. For uniform attribute noise, in which each attribute is flipped independently at random with the same probability, we present an algorithm that …


The 3-Tier Structured Access Protocol To Control Unfairness In Dqdb Mans, Lakshmana N. Kumar, Andreas D. Bovopoulos Jun 1992

The 3-Tier Structured Access Protocol To Control Unfairness In Dqdb Mans, Lakshmana N. Kumar, Andreas D. Bovopoulos

All Computer Science and Engineering Research

This paper addresses the unfairness problem appearing in 802.6-based DQDB MANs. Traffic load demand is characterized as low (below 0.4 of the channel capacity), normal (from 0.4 to 0.9 of the channel capacity) or heavy (greater than 0.9 of the channel capacity). At low loads the 802.6 protocol is acceptably fair. At normal loads, however, the protocol performance is markedly unfair. The unfairness is related to the latency in transporting a request. At heavy loads the unfairness is both latency-related and flooding-related. In this paper, both types of unfairness are carefully analyzed. As a control measure, a 3-Tier Structured Access …


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 5, May 1992, College Of Engineering And Computer Science, Wright State University May 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 5, May 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A six page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 4, April 1992, College Of Engineering And Computer Science, Wright State University Apr 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 4, April 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Implementation And Analysis Of Np-Complete Algorithms On A Distributed Memory Computer, Joel S. Garmon Mar 1992

Implementation And Analysis Of Np-Complete Algorithms On A Distributed Memory Computer, Joel S. Garmon

Theses and Dissertations

The purpose of this research is to explore methods used to parallelize NP-complete problems and the degree of improvement that can be realized using different methods of load balancing. A serial and four parallel A* branch and bound algorithms were implemented and executed on an Intel iPSC/2 hypercube computer. One parallel algorithm used a global, or centralized, list to store unfinished work and the other three parallel algorithms used a distributed list to store unfinished work locally on each processor. the three distributed list algorithms are: without load balancing, with load balancing, and with load balancing and work distribution. The …


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 3, March 1992, College Of Engineering And Computer Science, Wright State University Mar 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 3, March 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec Mar 1992

Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec

Theses and Dissertations

The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 2, February 1992, College Of Engineering And Computer Science, Wright State University Feb 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 2, February 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 1, January 1992, College Of Engineering And Computer Science, Wright State University Jan 1992

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 1, January 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A ten page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.


Porting Chorus To The Pa-Risc: Overall Evaluation, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru Jan 1992

Porting Chorus To The Pa-Risc: Overall Evaluation, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System kernel to the Hewlett-Packard 9000 Series 800 workstation. This document summarizes the matches and mis-matches between Chorus and the PA-RISC and outlines the general lessons learned during the project.

This document is intended for people who are interested in (a) the separation of machinedependent micro-kernel code from machine-independent micro-kernel code, (b) the interaction between operating system design and the PA-RISC architecture, and (c) the portability ofthe Chorus operating system.

The first report in the series, Porting Chorus to the PA-RISe: …


Porting Chorus To The Pa-Risc: Booting, Jon Inouye, Ravi Konuru, Jonathan Walpole, Marion Hakanson Jan 1992

Porting Chorus To The Pa-Risc: Booting, Jon Inouye, Ravi Konuru, Jonathan Walpole, Marion Hakanson

Computer Science Faculty Publications and Presentations

We started out with the low level Tut (HP-CX 2.0) boot code. One of our goals was to reuse as much of this code as possible, which would reduce the amount of low level code we would have to debug. This was very important, especially fiince the RP 9000/834 has a very complex I/O architecture and we lacked any sophisticated debugging tools. Writing the PA-Chorus boot code involved modifying the Tut code to match the Chorus startup sequence. In the remainder of this section, we present an overview of the PA-RISC boot mechanisms and the Chorus startup sequence. Sectlon 2 …


Porting Chorus To The Pa-Risc: Virtual Memory Manager, Jon Inouye, Marion Hakanson, Ravi Konuru, Jonathan Walpole Jan 1992

Porting Chorus To The Pa-Risc: Virtual Memory Manager, Jon Inouye, Marion Hakanson, Ravi Konuru, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document describes the port ofthe Chorus virtual memory manager to the Hewlett-Packard Precision Architecture rusc (PA-RISC) workstation. The information contained in this paper will be of interest to people who:

• intend to port the Chorus virtual memory section. • intend to port a virtual memory design to the Hewlett-Packard PA-RISC.

The reader is strongly encouraged to read the following PA-Chorus documents before reading this document:

• Technical Report CSE-92-3, Porting Chorus to the PA-RISC: Project Overview


Porting Chorus To The Pa-Risc: Project Overview, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru Jan 1992

Porting Chorus To The Pa-Risc: Project Overview, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation. This document presents an overview of the project, and outlines the other reports in the series and the relationships between them.