Engineering Commons^™

A Hardware Based Audio Event Detection System, Jacob Daniel Tobin

Masters Theses

Audio event detection and analysis is an important tool in many fields, from entertainment to security. Recognition technologies are used daily for parsing voice commands, tagging songs, and real time detection of crimes or other undesirable events. The system described in this work is a hardware based application of an audio detection system, implemented on an FPGA. It allows for the detection and characterization of gunshots and other events, such as breaking glass, by comparing a recorded audio sample to 20+ stored fingerprints in real time. Additionally, it has the ability to record flagged events and supports integration with mesh …

Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed

Masters Theses

Persons of visual impairment make up a growing segment of modern society. To cater to the special needs of these individuals, society ought to consider the design of special constructs to enable them to fulfill their daily necessities. This research proposes a new method for text extraction from indoor signage that will help persons of visual impairment maneuver in unfamiliar indoor environments, thus enhancing their independence and quality of life.

In this thesis, images are acquired through a video camera mounted on glasses of the walking person. Frames are then extracted and used in an integrated framework that applies Maximally …

A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader

Masters Theses

Due to modern DNA sequencing technologies vast amount of short DNA sequences known as short-reads is generated. Biologists need to be able to align the short-reads to a reference genome to be able to make scientific use of the data. Fast and accurate short-read aligner programs are needed to keep up with the pace at which this data is generated. Field Programmable Gate Arrays have been widely used to accelerate many data-intensive bioinformatics applications.

Burrows-Wheeler Transform has been used in the theory of string matching which has led to the development of many short-read alignment programs. This thesis presents a …

Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard

Theses and Dissertations

Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's …

Securing Network Processors With Hardware Monitors, Kekai Hu

Doctoral Dissertations

As an essential part of modern society, the Internet has fundamentally changed our lives during the last decade. Novel applications and technologies, such as online shopping, social networking, cloud computing, mobile networking, etc, have sprung up at an astonishing pace. These technologies not only influence modern life styles but also impact Internet infrastructure. Numerous new network applications and services require better programmability and flexibility for network devices, such as routers and switches. Since traditional fixed function network routers based on application specific integrated circuits (ASICs) have difficulty keeping pace with the growing demands of next-generation Internet applications, there is an …

An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija

Master's Theses

Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …

Danna A Neuromorphic Computing Vlsi Chip, Christopher Paul Daffron

Masters Theses

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons or synapses with programmable interconnections and parameters. Currently, DANNAs are implemented using a Field Programmable Gate Array (FPGA) and are constrained by this technology. To alleviate these constraints and introduce new and improved features, a semi-custom Very Large Scale Integration (VLSI) implementation has been created. This implementation improves upon the FPGA implementation in three key areas. The density of the array is improved, with 5,625 elements on a single …

Design & Development Of Fpga Based Vme Bus Controller, Himali Patel, Poornima Talwai

Innovative Research Publications IRP India

The VME bus interface Controller (VIC068A) is used to interface Local CPU bus and VME bus. VME Bus Controller is used in wide application areas where high reliability, good accuracy and high speed are desired to withstand industrial environment like nuclear power plant and process industries. VME Bus controller can configure as Master, Slave, Interrupt Handler, arbiter as well as power monitor. Commercial VME Bus interface controller chips are available from a few vendors and are very expensive. As time goes VME Bus Controller Chips become absolute and vendor support will not be provided. To solve part obsolescence problem and …

Address Space Translation For Fpga Accelerated Simulators, Michael Thaddeus Chamberlain

Theses and Dissertations

Microarchitectural simulation is needed to help explore the large design space of new computer systems. These simulations are taking increasingly longer amounts of time to run due to the increasing complexity of modern processors. Co-simulation and high level synthesis are promising fields to improve the overall time required for microarchitectural simulators, and can contribute to low design times and fast simulation speeds permitting a larger range of design space exploration. While promising, co-simulation techniques must find effective ways to map the host memory address space to the FPGA memory address space to be able to correctly transfer simulation data between …

Preemptive Placement And Routing For In-Field Fpga Repair, Joshua E. Jensen

Theses and Dissertations

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This thesis presents a method for preemptively preparing to repair FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found …

Designing And Implementing A Reliable Thermal Monitoring System Based On The 1-Wire Protocol On Fpga For A Leo Satellite, Reza Omidi Gosheblagh, Karim Mohammadi

Turkish Journal of Electrical Engineering and Computer Sciences

Thermal control and monitoring is one of the most important factors in the design of satellite systems. An appropriate thermal design should make sure that the satellite's sensitive components remain in their nominated range, even under the vacuum condition of outer space. To achieve this purpose, a reliable and stable monitoring system is required. This paper proposes a monitoring system based on the 1-wire protocol, which provides the reliability requirements in the sensor networking and bus controller sections. In the networking section, we outline some practical topologies and discuss on their complexity and reliability. Despite the fact that the point-to-point …