Engineering Commons^™

Fpga Security Techniques With Applications To Cloud And Multi-Tenant Use Cases, Xiang Li

Doctoral Dissertations

Field programmable gate arrays (FPGAs) are integrated circuits that consist of programmable logic that a user can configure and deploy for applications such as hardware emulation and accelerating high performance computing. In recent years, the emergence of FPGAs in the cloud has led to research on multi-tenant FPGAs. In a multi-tenant scenario, the same FPGA fabric is shared among multiple users, or among multiple untrusting IP cores. Multi-tenancy has economic benefits, largely due to improvements in resource utilization, but also brings new security concerns since the tenants could behave maliciously. Although the tenants sharing an FPGA are logically isolated from …

A Sindy Hardware Accelerator For Efficient System Identification On Edge Devices, Michael Sean Gallagher

Master's Theses

The SINDy (Sparse Identification of Non-linear Dynamics) algorithm is a method of turning a set of data representing non-linear dynamics into a much smaller set of equations comprised of non-linear functions summed together. This provides a human readable system model the represents the dynamic system analyzed. The SINDy algorithm is important for a variety of applications, including high precision industrial and robotic applications. A Hardware Accelerator was designed to decrease the time spent doing calculations. This thesis proposes an efficient hardware accelerator approach for a broad range of applications that use SINDy and similar system identification algorithms. The accelerator is …

Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays In Fpgas, Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy

Electrical and Computer Engineering Faculty Publications

Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply–Accumulate Array (SMA) as its computational brain. In this paper, we investigate the faulty output characterization of an SMA in a real silicon FPGA board. Experiments were run on a single Zybo Z7-20 board to control for process variation at nominal voltage and in small batches to control for temperature. The FPGA is rated up to 800 MHz in the data sheet due to the max frequency of the PLL, but the …

Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner

Faculty Publications

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

A Design Strategy To Improve Machine Learning Resiliency Of Physically Unclonable Functions Using Modulus Process, Yuqiu Jiang

Theses and Dissertations

Physically unclonable functions (PUFs) are hardware security primitives that utilize non-reproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity …

Normalized Linearly-Combined Chaotic System: Design, Analysis, Implementation And Application, Md Sakib Hasan, Anurag Dhungel, Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain

Faculty and Student Publications

This work presents a general framework for developing a multi-parameter 1-D chaotic system for uniform and robust chaotic operation across the parameter space. This is important for diverse practical applications where parameter disturbance may cause degradation or even complete disappearance of chaotic properties. The wide uninterrupted chaotic range and improved chaotic properties are demonstrated with the aid of stability analysis, bifurcation diagram, Lyapunov exponent (LE), Kolmogorov entropy, Shannon entropy, and correlation coefficient. We also demonstrate the proposed system’s amenability to cascading for further performance improvement. We introduce an efficient Field-Programmable Gate Array (FPGA)-based implementation and validate its chaotic properties using …

Development Of The Digital Signal Processing For The Space Weather Probes Version 2 Sensor Using The Matlab/Simulink Environment, Benjamin J. Lewis

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Space Weather Probes (SWP) is an instrument that provides measurements of the plasma environment of the ionosphere. SWP was flown on the Scintillation Prediction Observation Task (SPORT) mission, a joint mission between the United States of America and Brazil. This thesis will develop the digital signal processing (DSP) hardware design for the Space Weather Probes version 2 (SWP2). The data from these instruments will be used to determine the density and temperature of the local plasma, as well as the electric field in the local plasma. This thesis presents the design and testing of the DSP designs for all of …

A Reconfigurable Architecture For Matrix Multiplication For Low Power Applications, Jeffrey Love

Electrical and Computer Engineering ETDs

This thesis presents a hardware architecture for performing matrix multiplication via a systolic array to reduce time complexity and power consumption. The proposed architecture, the Neural Network Accelerator (NNA), was designed in Verilog HDL to perform 8-bit multiplication to reduce the resources required to implement the NNA on low-power FPGAs. The NNA’s open architecture is designed to support radiation test for fault tolerant designs targeting space applications. Commercial hardware architecture information is not public knowledge, which led us to build our own matrix multiplication architecture so that we could later study its feasibility for space applications.

The NNA was compared …

Approximate Computing Based Processing Of Mea Signals On Fpga, Mohammad Emad Hassan

Dissertations

The Microelectrode Array (MEA) is a collection of parallel electrodes that may measure the extracellular potential of nearby neurons. It is a crucial tool in neuroscience for researching the structure, operation, and behavior of neural networks. Using sophisticated signal processing techniques and architectural templates, the task of processing and evaluating the data streams obtained from MEAs is a computationally demanding one that needs time and parallel processing.

This thesis proposes enhancing the capability of MEA signal processing systems by using approximate computing-based algorithms. These algorithms can be implemented in systems that process parallel MEA channels using the Field Programmable Gate …

Integration Of Digital Signal Processing Block In Symbiflow Fpga Toolchain For Artix-7 Devices, Andrew T. Hartnett

Masters Theses

The open-source community is a valuable resource for many hobbyists and researchers interested in collaborating and contributing towards publicly available tools. In the area of field programmable gate arrays (FPGAs) this is no exception. Contributors seek to reverse-engineer the functions of large proprietary FPGA devices. An interesting challenge for open-source FPGA engineers has been reverse-engineering the operation and bitstreams of digital signal processing (DSP) blocks located in FPGAs. SymbiFlow is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. For SymbiFlow, mapping logical multipliers to DSP blocks and generating DSP block bitstreams …

Design And Implementation Of A Low Cost And Portable Tactile Stimulator, Coşkun Kazma, Vecdi̇ Emre Levent, Merve Çardak, Ni̇zametti̇n Aydin

Turkish Journal of Electrical Engineering and Computer Sciences

When central nervous system has a problem, somatic area I and II respond to stimulation differently. Therefore, it is possible to identify some of the central nervous diseases when somatosensory on the fingertip is stimulated and responses are recorded and analyzed. We designed a system to stimulate the mechanoreceptors on fingertips. It is composed of a mechanical system for fingertip stimulation, an embedded controller, a control computer, and a software to control overall operation. During test, mechanoreceptors are stimulated according to the test protocols. Individuals' answers are recorded to be evaluated by the developed software. In this study, several design …

Networked Digital Predictive Control For Modular Dc-Dc Converters, Castulo Aaron De La O Pérez

Theses and Dissertations

The concept of power electronics building blocks (PEBB) has driven advancements in highly modularized converter systems with many identical subsystems. PEBBs are distributed subsets of converter systems and thus require communication with a control system for their coordination. For this type of system, the communication latency with hard deterministic deadlines is the driving attribute of communication system requirements. However, inherent communication requirements for PEBB-based converter systems also provide opportunities for coordination of energy flow.

Leveraging developments in Gigabit serial communication channels, a control and communication platform architecture for distributed control schemes based on the 2D-Torus communication network topology was developed …

Cmos Sensor Image-Acquisition And Image- Processing Control System Architecture, Haruka Kido

Electrical Engineering Student Publications

This report demonstrates an assessment of a PCAM camera module’s OV5640 CMOS sensor image-acquisition electrical circuit network system and hardware implementation for associated FPGA-modulated image-processing techniques using Digilent’s Zybo Z7-20 development board’s FPGA (Zynq 7000 SoC). By comparison between the control system architectures of 2 proposed Active Pixel CMOS sensor electrical network configurations (both 1 Row 1-Column Select Implementations) using electrical network transfer function derivations, time responses, Root Locus Plots, Bode Plots, and their system characteristics as preliminary analyses, FPGA-modulation of the CMOS sensor through image format adjustment is developed as an example of image properties adjustment enabled by the …

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett

Masters Theses

The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.

The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …

Real Time Simulation And Hardware In The Loop Methods For Power Electronics Power Distribution Systems, Michele Difronzo

Theses and Dissertations

System level testing of Power Electronics Power Distribution Systems (PEPDS) can be challenging when fine temporal resolution is required (time step below 100-200ns). In the recent years, our research group has proposed various methods to simulate in real-time PEPDS using FPGAs and time step as small as 50ns. While the proposed methods allow achieving the desired temporal resolution, they are extremely demanding in terms of resources usage and the size of the PEPDS that can be simulated on a single FPGA is strongly limited.

In this dissertation -work that takes as an example application the US Navy electric Ship Zonal …

High Frequency Injection Sensorless Control For A Permanent Magnet Synchronous Machine Driven By An Fpga Controlled Sic Inverter, Jared Walden

Masters Theses

As motor drive inverters continue to employ Silicon Carbide (SiC) and Gallium Nitride (GaN) devices for power density improvements, sensorless motor control strategies can be developed with field-programmable gate arrays (FPGA) to take advantage of high inverter switching frequencies. Through the FPGA’s parallel processing capabilities, a high control bandwidth sensorless control algorithm can be employed. Sensorless motor control offers cost reductions through the elimination of mechanical position sensors or more reliable electric drive systems by providing additional position and speed information of the electric motor. Back electromotive force (EMF) estimation or model-based methods used for motor control provide precise sensorless …

Bibliometric Review Of Fpga Based Implementation Of Cnn, Priti Shahane, Piyush Tyagi, Purba Saha, Shravan Sainath, Swanand Bedekar

Library Philosophy and Practice (e-journal)

Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources …

Shift Register Puf Implementation On An Fpga, Sriram Thotakura

Electrical and Computer Engineering ETDs

In this thesis, a novel shift register-based physical unclonable function (PUF), called SRP, is proposed. The PUF is implemented on an FPGA and leverages the internal delay variations introduced by within-die process variations that occur within the Look-up tables (LUTs), routing and switches of the FPGA. PUFs are designed to generate bitstrings and keys on-the-fly that are device-specific (unique), random and reproducible. PUFs eliminate the need for a specialized (secure) non-volatile memory(NVM) to store the secret keys. This reduces the total cost of chips and systems, particularly those used in the Internet of Things, where it is common for systems …

Very Low Frequency Electrical Impedance Tomography Image Reconstruction System Using Fpga Software-Hardware Co-Design, Monali Sinare

Culminating Projects in Electrical Engineering

Electrical Impedance Tomography (EIT) is an imaging technique which is noninvasive and uses the internal conductivity distribution of the object of interest to form a tomographic image. It is performed by applying electrodes to the surface of the object. An alternating current up to frequency 10kHz is applied through a pair of electrodes, and the induced voltage is measured on other electrodes. These current and voltage values are used to reconstruct the internal conductivity distribution. The EIT imaging is increasingly getting used in clinical applications, as it is safer, portable, and low cost if compared with available imaging technologies used …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …

System Design And Implementation For Hybrid Network Function Virtualization, Xuzhi Zhang

Doctoral Dissertations

With the application of virtualization technology in computer networks, many new research areas and techniques have been explored, such as network function virtualization (NFV). A significant benefit of virtualization is that it reduces the cost of a network system and increases its flexibility. Due to the increasing complexity of the network environment and constantly improving network scale and bandwidth, it is imperative to aim for higher performance, extensibility, and flexibility in the future network systems. In this dissertation, hybrid NFV platforms applying virtualization technology are proposed. We further explore the techniques used to improve the performance, scalability and resilience of …

Hardware Development For The Generation Of Large-Volume High Pressure Plasma By Spatiotemporal Control Of Space Charge, Nikhil Boothpur

Electrical & Computer Engineering Theses & Dissertations

While generating a plasma under laboratory conditions, any attempt to scale the pressure and volume leads to instabilities due to the build-up of localized space-charge. This poses a challenge in the design of the discharge chamber, type of excitation field, and the type of gas that is used in the discharge. This work investigates a spatially and temporally varying electric field to control the formation of space-charge in large-volume (greater than 5 mm in the smallest dimension) near atmospheric pressure. The simulations show that in a space-charge dominated transport, the charged species disperse both in azimuthal and radial directions in …

End-To-End Direct Digital Synthesis Simulation And Mathematical Model To Minimize Quantization Effects Of Digital Signal Generation, Pranav R. Patel, Richard K. Martin

Faculty Publications

Direct digital synthesis (DDS) architectures are becoming more prevalent as modern digital-to-analog converter (DAC) and programmable logic devices evolve to support higher bandwidths. The DDS architecture provides the benefit of digital control but at a cost of generating spurious content in the spectrum. The generated spurious content may cause intermodulation distortion preventing proper demodulation of the received signal. The distortion may also interfere with the neighboring frequency bands. This article presents the various DDS architectures and explores the DDS architecture which provides the most digital reconfigurability with the lowest spurious content. End-to-end analytical equations, numerical and mathematical models are developed …

Data Processing Electronics For An Ultra-Fast Single-Photon Counting Camera, Jackson Hyde

McKelvey School of Engineering Theses & Dissertations

Localizing photon arrivals with high spatial (megapixel) and temporal (sub-nanosecond) resolution would be transformative for a number of applications, including single-molecule super-resolution fluorescence microscopy. Here, the Data Processing Field Programmable Gate Array (FPGA) is developed as an ultra-fast computational platform built on an FPGA for a microchannel plate (MCP)-photomultiplier tube (PMT) based single-photon counting camera. Each photon is converted by the MCP-PMT into an electron cloud that generates current pulses across a 50×50 cross-strip anode. The Data Processing FPGA executes a massively parallel center-of-gravity coordinate determination algorithm on the digitized current pulses to determine a 2D position and time of …

Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse

Masters Theses

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …

Medusa: A Low-Cost, 16-Channel Neuromodulation Platform With Arbitrary Waveform Generation, Fnu Tala, Benjamin C. Johnson

Electrical and Computer Engineering Faculty Publications and Presentations

Neural stimulation systems are used to modulate electrically excitable tissue to interrogate neural circuit function or provide therapeutic benefit. Conventional stimulation systems are expensive and limited in functionality to standard stimulation waveforms, and they are bad for high frequency stimulation. We present MEDUSA, a system that enables new research applications that can leverage multi-channel, arbitrary stimulation waveforms. MEDUSA is low cost and uses commercially available components for widespread adoption. MEDUSA is comprised of a PC interface, an FPGA for precise timing control, and eight bipolar current sources that can each address up to 16 electrodes. The current sources have a …

An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke

Graduate Theses and Dissertations

The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …

Trustworthy Systems And Protocols For The Internet Of Things, Arman Pouraghily

Doctoral Dissertations

Processor-based embedded systems are integrated into many aspects of everyday life such as industrial control, automotive systems, healthcare, the Internet of Things, etc. As Moore’s law progresses, these embedded systems have moved from simple microcontrollers to full-scale embedded computing systems with multiple processor cores and operating systems support. At the same time, the security of these devices has also become a key concern. Our main focus in this work is the security and privacy of the embedded systems used in IoT systems. In the first part of this work, we take a look at the security of embedded systems from …