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Articles 8041 - 8070 of 10021
Full-Text Articles in Entire DC Network
Reporter - March 25th 1988, Rit Reporter Staff
Reporter - March 25th 1988, Rit Reporter Staff
University Publications
No abstract provided.
R.I.T. News & Events - March 24, 1988, University News Services, Rochester Institute Of Technology
R.I.T. News & Events - March 24, 1988, University News Services, Rochester Institute Of Technology
University Publications
No abstract provided.
Reporter - March 18th 1988, Rit Reporter Staff
Reporter - March 18th 1988, Rit Reporter Staff
University Publications
No abstract provided.
R.I.T. News & Events - March 10, 1988, University News Services, Rochester Institute Of Technology
R.I.T. News & Events - March 10, 1988, University News Services, Rochester Institute Of Technology
University Publications
No abstract provided.
A Test Chip Approach To Routine Process Control, Eric J. Meisenzahl
A Test Chip Approach To Routine Process Control, Eric J. Meisenzahl
Theses
A procedure for determining process control and yield prediction is presented which primarily serves to evaluate the quality and repeatability of critical fabrication steps, but also serves to quantify process capabilities and limitations for future design considerations. This can be accomplished through the use of a specially designed test chip. The test chip is designed for use in determining the process control and fabrication capability of the Microelectronic Engineering Department's fabrication lab of Rochester Institute of Technology.
Gca 4800 Dsn Wafer Stepper, Matthew J. Comard
Gca 4800 Dsn Wafer Stepper, Matthew J. Comard
Theses
The following work lays the foundation for the further development of high resolution photolithography at RIT using a GCA 4800 DSW wafer stepper. It has been determined experimentally that . the machine is presently capable of printing 1.4 micrometer lines and spaces with and exposure latitude of 10% over the entire wafer. The stage precision is within the +0.2 micron spec, and the system registration is within the + 0.35 micron specification. The stage orthogonality has been corrected so that it is within the + 0.5 arc second specification. Optical distortion is within its spec of + 0.2 microns, while …
Computer Animation Design And Execution: Integrating Poetry And Technology, Catherine Haven Kirby
Computer Animation Design And Execution: Integrating Poetry And Technology, Catherine Haven Kirby
Theses
None provided.
Reporter - February 19th 1988, Rit Reporter Staff
Reporter - February 19th 1988, Rit Reporter Staff
University Publications
No abstract provided.
R.I.T. News & Events - February 18, 1988, University News Services, Rochester Institute Of Technology
R.I.T. News & Events - February 18, 1988, University News Services, Rochester Institute Of Technology
University Publications
No abstract provided.
Reporter - February 12th 1988, Rit Reporter Staff
Reporter - February 12th 1988, Rit Reporter Staff
University Publications
No abstract provided.
Reporter - February 5th 1988, Rit Reporter Staff
Reporter - February 5th 1988, Rit Reporter Staff
University Publications
No abstract provided.
R.I.T. News & Events - February 4, 1988, University News Services, Rochester Institute Of Technology
R.I.T. News & Events - February 4, 1988, University News Services, Rochester Institute Of Technology
University Publications
No abstract provided.
A Model For Non-Image Area Of Offset Lithographic Process, Vinay Chhajlani
A Model For Non-Image Area Of Offset Lithographic Process, Vinay Chhajlani
Theses
Lithography is the most common printing process. However, very little is known about the theory of lithography. Pressroom practices have evolved more out of experience than on the basis of any theory. The objective of this paper is to develop a mathematical model for the non-image area of the offset lithographic plate. A model of this kind would provide a rationalization for the observed behavior in lithographic process. The study concentrates on the various materials and the phenomena involved. Properties of aluminum oxide surface and gum arabic that make them suitable for the process have been presented. Rheological properties of …
Reporter - January 29th 1988, Rit Reporter Staff
Reporter - January 29th 1988, Rit Reporter Staff
University Publications
No abstract provided.
R.I.T. News & Events - January 21, 1988, University News Services, Rochester Institute Of Technology
R.I.T. News & Events - January 21, 1988, University News Services, Rochester Institute Of Technology
University Publications
No abstract provided.
R.I.T. News & Events - January 7, 1988, University News Services, Rochester Institute Of Technology
R.I.T. News & Events - January 7, 1988, University News Services, Rochester Institute Of Technology
University Publications
No abstract provided.
Radiation Effects On Pmos Devices, Camille G. Bates
Radiation Effects On Pmos Devices, Camille G. Bates
Journal of the Microelectronic Engineering Conference
A Cesium—137 gamma radiation source was used to irradiate PMOS capacitors and transistors with doses of 7.50E4, 1.50E5, 3.0E5. The devices were tested for C-V and I-V data before and after irradiation. Results show that all doses created changes in the electrical characteristics, however comparison to literature was I inconclusive.
Boron Solid Source Characterization, Kelly Baycura
Boron Solid Source Characterization, Kelly Baycura
Journal of the Microelectronic Engineering Conference
Standard Oil’s BN—975 planar diffusion sources were used to fabricate integrated resistors. Dopant transfer was done in a N2:02:H2 ambient at 975 C. Two methods of removing the crystal defect layer formed at the surface, low temperature oxidation (LTO) and a nitric acid soak, were evaluated. Successful layer removal was achieved with the LTO. The nitric acid soak met with limited success.
Design Of A Four-Bit Microprocessor A.L.U Using Pmos 10-Um Metal Gate Technology, John F. Bonaker
Design Of A Four-Bit Microprocessor A.L.U Using Pmos 10-Um Metal Gate Technology, John F. Bonaker
Journal of the Microelectronic Engineering Conference
A four-bit ALU chip based on a metal gate PMOS process and 10-urn minimum geometries was designed. The operations performed by the ALU included ADD w/carry, SUBTRACT(2’s complement), INCREMENT, DECREMENT, and the logic functions AND, OR, XOR, and COMPLEMENT. Due to space limitations no data or shift registers were included on the chip. PMOS NOR gates and inverters were used in the hardware Implementation of the logic design. The ALU chip was laid out by using the ICE (Integrated Circuit Editor) design tool.
Cmos Pla Layout Generation, Christopher D. Bryant
Cmos Pla Layout Generation, Christopher D. Bryant
Journal of the Microelectronic Engineering Conference
A dynamic AND - dynamic OR type of PLA was designed using a CMOS process and the layout was done on a CALMA system using l.5um design rules. A PLA with 200 transistors was completed and can be used to perform desired logic functions.
A Method To Improve Step Coverage Of Conventional Positive Working Photoresist, Dave Brzozowy
A Method To Improve Step Coverage Of Conventional Positive Working Photoresist, Dave Brzozowy
Journal of the Microelectronic Engineering Conference
Positive resist coated wafers were Immersed in a dilute alkaline base developer, such as 5:1 AZ351, for a short period of time prior to exposure. The purpose of this sequence was to improve development rate discrimination of conventional positive photoresist, which will enhance step coverage. A SEM comparison of a 5 mIcron line/space pair pattern of AZ13SO resist on a 1.2 micron step, showed this pre-treatment yields improved step coverage compared to a conventional process.
Multilevel Metallization At Rit, Manuel N. Carneiro
Multilevel Metallization At Rit, Manuel N. Carneiro
Journal of the Microelectronic Engineering Conference
This project was a preliminary study of an aluminum/dielectric/aluminum multilayer metallizatiOn scheme. Polyimide and spin on glass were compared using high frequency CV analysis on fabricated capacitors. The simple processing involved showed that good crack-free and adhesive fil s could be formed with both materials although the polyimide was the more ideal CV characteristics. Test masks were generated to measure via resistance and dielectric breakdown in a bi-level structure. The Spin on Glass processing was unsuccessful because of underetching of vias. The polyimide processing was successful displaying good breakdown characteristics but high via resistances.
Automated Design Rule Checking, Carl E. Conrad
Automated Design Rule Checking, Carl E. Conrad
Journal of the Microelectronic Engineering Conference
A Fortran Coded Design Rule Checker was written to analyze the output file of the RIT Integrated Circuit Editor (ICE) program. The design rules for the RIT 4LEVELPMOS process have been successfully implemented for a die size of 1900 by 1900 square micrometers.
Determination Of Minority Carrier Lifetimes Using The Capacitance-Time Technique, Patrick M. Denero
Determination Of Minority Carrier Lifetimes Using The Capacitance-Time Technique, Patrick M. Denero
Journal of the Microelectronic Engineering Conference
Capacitance—Time (C—T) plots were generated using a Micromanipulator model 410 CV system with a Yokogawa 3022 A4 x—Y recorder (with time base activated). MOS capacitors were pulsed instantaneously from accumulation into deep—depletion. The capacitance was then recorded as the samples relaxed back to their equilibrium state (Cmin). The method used to analyze the C—T data was known as a ZERBST analysis. A FORTRAN program was created to handle the differentiating required for the ZERBST plot. Preliminary results indicate that this set—up will accurately determine minority carrier lifetimes.
Response Surface Methodology Using Experimental Design, Jamshed H. Dubash
Response Surface Methodology Using Experimental Design, Jamshed H. Dubash
Journal of the Microelectronic Engineering Conference
A Central—Composite Full Factorial design was performed in aiming to optimize the develop and bake processes on KTI 820 resist and KTI 934 developer using the GCA Wafertrac. The responses looked at were critical dimension and resist thickness after development with the independent variables of postbake temperature, postbake time and developer time. Analysis of the data was done using SAS as a software tool.
Development And Evaluation Of Chlorinated Gate Oxides, David H. Fatke
Development And Evaluation Of Chlorinated Gate Oxides, David H. Fatke
Journal of the Microelectronic Engineering Conference
The effect of TCA tube cleaning and oxidation on mobile ion contamination for the growth of gate oxides was Investigated. It was found that the TCA tube clean had a major effect in reduction of mobile ions, while the TCA gate oxide process employed had a negligible effect.
Characterization Of The Perkin-Elmer Model 140 Projection Aligner Exposure Source And Modeling Of Resist Profiles, Arthur Shaun Francomacaro
Characterization Of The Perkin-Elmer Model 140 Projection Aligner Exposure Source And Modeling Of Resist Profiles, Arthur Shaun Francomacaro
Journal of the Microelectronic Engineering Conference
A correlation between scan speed and exposure dose, was obtained for the Perkin-Elmer Model 140 Projection Aligner to Facilitate accurate resist profile modeling. A photovoltaic cell collector with filtering was mounted on a modified wafer chuck to acquire exposure data. The relationship between scan speed and exposure was found to be linear when plotted on log-log scale and predictable to within 57~. Lines of 1.4 urn in Shipley 1400-27 resist and 1.6 urn in KTI 820 resist were successfully imaged. Modeling of the scanner’s output aerial image via PROSIM (Perkin- Elmer resist profile model) was performed with fair results.
Design Of A 4-Bit Pmos Parallel Comparator A/D Converter, Amel Gaddo
Design Of A 4-Bit Pmos Parallel Comparator A/D Converter, Amel Gaddo
Journal of the Microelectronic Engineering Conference
This project dealt with the design of a 4-bit PMOS parallel comparator analog-to-digital converter. Using a predesigned comparator circuit, the rest of the logic was completed. Circuit analysis was performed using SPICE simulation. Circuit layout was done using integrated Circuit Editor (ICE). The PMOS process consists of four masking levels; diffusion, thin oxide, contact cuts, and metal.
Fabrication Of A Single Level Metal Ccd Shift Register, John P. Gardner
Fabrication Of A Single Level Metal Ccd Shift Register, John P. Gardner
Journal of the Microelectronic Engineering Conference
Using a “shadow mask” technique, a single level metal 3-phase CCD shift register was fabricated with electrode separations of 2 microns. Testing is pending at this time.
Software Analysis Of Capacitance-Voltage Measurements, Richard A. German
Software Analysis Of Capacitance-Voltage Measurements, Richard A. German
Journal of the Microelectronic Engineering Conference
A computer program called CVPLOT, used at RIT to aid in the analysis of metal—oxide—semiconductor (MOS) capacitors, was recoded from REGIS graphics into the VAX Graphical Kernel System (GKS) allowing the user to obtain hardcopy plots of high and low frequency capacitance voltage curves from an HP—Plotter, LNO3 Laser Printer, and LA100 Line Printer. The revised program also allows changes to be made in the values of the ‘non—ideal’ (a nonzero flatband shift) parameters while subsequently observing the shift in the curve as a result of these changes. Curves for three different values of either substrate doping, gate oxide thickness, …