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Xtreme-Noc: Extreme Gradient Boosting Based Latency Model For Network-On-Chip Architectures, Ilma Sheriff
Xtreme-Noc: Extreme Gradient Boosting Based Latency Model For Network-On-Chip Architectures, Ilma Sheriff
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Multiprocessor System-on-Chip (MPSoC) integrating heterogeneous processing elements (CPU, GPU, Accelerators, memory, I/O modules ,etc.) are the de-facto design choice to meet the ever-increasing performance/Watt requirements from modern computing machines. Although at consumer level the number of processing elements (PE) are limited to 8-16, for high end servers, the number of PEs can scale up to hundreds. A Network-on-Chip (NoC) is a microscale network that facilitates the packetized communication among the PEs in such complex computational systems. Due to the heterogeneous integration of the cores, execution of diverse (serial and parallel) applications on the PEs, application mapping strategies, and many other …