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Full-Text Articles in Nanoscience and Nanotechnology
A New Method For The Removal Of Parasitic Capacitances From Sub-100nm Mosfets Using Low-Noise Split Capacitance-Voltage Measurements, Daniel R. Steinke
A New Method For The Removal Of Parasitic Capacitances From Sub-100nm Mosfets Using Low-Noise Split Capacitance-Voltage Measurements, Daniel R. Steinke
Legacy Theses & Dissertations (2009 - 2024)
The physical shape of MOSFETs and the processing involved in their fabrication give rise to parasitic capacitances. These capacitances are typically small compared to the intrinsic channel capacitance of the device, but as MOSFETs scale into the sub-100nm gate length range, the parasitic capacitances become a significant percentage of the overall measured capacitance, resulting in a source of error in the analysis of these devices. The purpose of this work is to describe these parasitic capacitances and their origin in MOSFET structures and to propose a method for their removal for analysis. The experimental devices used for this work are …
High-K Gate Stack On Compound Semiconductor Channel Materials For Low Power, High Performance Digital Logic Applications, Rama Kambhampati
High-K Gate Stack On Compound Semiconductor Channel Materials For Low Power, High Performance Digital Logic Applications, Rama Kambhampati
Legacy Theses & Dissertations (2009 - 2024)
Group III-V compound semiconductors such as InGaAs and InGaSb are actively being considered as channel materials for low power, high performance digital logic applications due to superior carrier transport properties such as mobility and saturation velocity. The high density of interface states at high-k dielectric and III-V interface that results in pinning of Fermi level is one of the major challenges that need to be addressed before III-V CMOS becomes a mainstream technology.