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Full-Text Articles in Nanoscience and Nanotechnology
Low-Temperature Fabrication Process For Integrated High-Aspect Ratio Metal Oxide Nanostructure Semiconductor Gas Sensors, William Paul Clavijo
Low-Temperature Fabrication Process For Integrated High-Aspect Ratio Metal Oxide Nanostructure Semiconductor Gas Sensors, William Paul Clavijo
Theses and Dissertations
This work presents a new low-temperature fabrication process of metal oxide nanostructures that allows high-aspect ratio zinc oxide (ZnO) and titanium dioxide (TiO2) nanowires and nanotubes to be readily integrated with microelectronic devices for sensor applications. This process relies on a new method of forming a close-packed array of self-assembled high-aspect-ratio nanopores in an anodized aluminum oxide (AAO) template in a thin (2.5 µm) aluminum film deposited on a silicon and lithium niobate substrate (LiNbO3). This technique is in sharp contrast to traditional free-standing thick film methods and the use of an integrated thin aluminum film …
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Development Of Iii-V P-Mosfets With High-Kappa Gate Stack For Future Cmos Applications, Padmaja Nagaiah
Legacy Theses & Dissertations (2009 - 2024)
As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport …
High-K Gate Stack On Compound Semiconductor Channel Materials For Low Power, High Performance Digital Logic Applications, Rama Kambhampati
High-K Gate Stack On Compound Semiconductor Channel Materials For Low Power, High Performance Digital Logic Applications, Rama Kambhampati
Legacy Theses & Dissertations (2009 - 2024)
Group III-V compound semiconductors such as InGaAs and InGaSb are actively being considered as channel materials for low power, high performance digital logic applications due to superior carrier transport properties such as mobility and saturation velocity. The high density of interface states at high-k dielectric and III-V interface that results in pinning of Fermi level is one of the major challenges that need to be addressed before III-V CMOS becomes a mainstream technology.
A New Method For The Removal Of Parasitic Capacitances From Sub-100nm Mosfets Using Low-Noise Split Capacitance-Voltage Measurements, Daniel R. Steinke
A New Method For The Removal Of Parasitic Capacitances From Sub-100nm Mosfets Using Low-Noise Split Capacitance-Voltage Measurements, Daniel R. Steinke
Legacy Theses & Dissertations (2009 - 2024)
The physical shape of MOSFETs and the processing involved in their fabrication give rise to parasitic capacitances. These capacitances are typically small compared to the intrinsic channel capacitance of the device, but as MOSFETs scale into the sub-100nm gate length range, the parasitic capacitances become a significant percentage of the overall measured capacitance, resulting in a source of error in the analysis of these devices. The purpose of this work is to describe these parasitic capacitances and their origin in MOSFET structures and to propose a method for their removal for analysis. The experimental devices used for this work are …