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FIELD-EFFECT TRANSISTOR; HIGH-PERFORMANCE ELECTRONICS; POROUS ALUMINA; ARRAYS; LITHOGRAPHY; FABRICATION; TEMPLATES; CIRCUITS; CONTACT; SILICON
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Full-Text Articles in Nanoscience and Nanotechnology
Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy Fisher, David B. Janes
Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy Fisher, David B. Janes
Robert A Sayer
The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.