VLSI and Circuits, Embedded and Hardware Systems Commons^™

Critical Area Driven Dummy Fill Insertion To Improve Manufacturing Yield, Nishant Dhumane

Masters Theses 1911 - February 2014

Non-planar surface may cause incorrect transfer of patterns during lithography. In today’s IC manufacturing, chemical mechanical polishing (CMP) is used for topographical planarization. Since polish rates for metals and oxides are different, dummy metal fills in layout is used to minimize post-CMP thickness variability. Traditional metal fill solutions focus on satisfying density target determined by layout density analysis techniques. These solutions may potentially reduce yield by increasing probability of failure (POF) due to particulate defects and also impact design performance. Layout design solutions that minimize POF and also improve surface planarity via dummy fill insertions have competing requirements for line …

Towards Logic Functions As The Device Using Spin Wave Functions Nanofabric, Prasad Shabadi

Masters Theses 1911 - February 2014

As CMOS technology scaling is fast approaching its fundamental limits, several new nano-electronic devices have been proposed as possible alternatives to MOSFETs. Research on emerging devices mainly focusses on improving the intrinsic characteristics of these single devices keeping the overall integration approach fairly conventional. However, due to high logic complexity and wiring requirements, the overall system-level power, performance and area do not scale proportional to that of individual devices.

Thereby, we propose a fundamental shift in mindset, to make the devices themselves more functional than simple switches. Our goal in this thesis is to develop a new nanoscale fabric paradigm …