VLSI and Circuits, Embedded and Hardware Systems Commons^™

Design And Analysis Of A Discrete, Pcb-Level Low-Power, Microwave Cross-Coupled Differential Lc Voltage-Controlled Oscillator, Pavin Singh Virdee

Master's Theses

Radio Frequency (RF) and Microwave devices are typically implemented in Integrated Circuit (IC) form to minimize parasitics, increase precision and tolerances, and minimize size. Although IC fabrication for students and independent engineers is cost-prohibitive, an abundance of low-cost, easily accessible printed circuit board (PCB) and electronic component manufacturers allows affordable PCB fabrication.

While nearly all microwave voltage-controlled oscillator (VCO) designs are IC-based, this study presents a discrete PCB-level cross-coupled, differential LC VCO to demonstrate this more affordable and accessible approach. This thesis presents a 65 mW, discrete component VCO PCB with industry-comparable RF performance. A phase noise of -103.7 dBc/Hz …

Indoor Positioning Using Synchronized Ultrasonic Ofdma Signals, Julian Bartolone

Master's Theses

This paper proposes a method of short-range indoor localization using differential phase measurements of synchronized two-tone ultrasonic signals in an Orthogonal Frequency Multiple Access (OFDMA) scheme. This indoor positioning system (IPS) operates at an ultrasonic frequency of approximately 40kHz and synchronizes using an infrared signal. The OFDMA scheme allows for a receiver to process the signals from multiple transmitters continuously without the signals interfering with each other. The phases of the signals are measured using Goertzel Filters, allowing for low-complexity frequency content analysis. A MATLAB simulation using the proposed localization method is performed using four transmitter nodes in the corners …

Design And Characterization Of Standard Cell Library Using Finfets, Phanindra Datta Sadhu

Master's Theses

The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the transistor's breakdown caused by short channel effects. An alternative solution to this is the FinFET transistor technology, where the gate of the transistor is a three dimensional fin that surrounds the transistor and prevents the breakdown caused by scaling …

Design Of An Ultra-Wideband Frequency-Modulated Continuous Wave Short Range Radar System For Extending Independent Living, Toai-Chi Nguyen

Master's Theses

Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design …

Cmos Design Of An 8-Bit 1ms/S Successive Approximation Register Adc, Ameya Vivekanand Ganguli

Master's Theses

Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.

This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an …

Analog Single Sideband-Pulse Width Modulation Processor For Parametric Acoustic Arrays, Vikrant A. Marathe

Master's Theses

Parametric acoustic arrays are ultrasonic-based loudspeakers that produce highly directive audio. The audio must first be preprocessed and modulated into an ultrasonic carrier before being emitted into the air, where it will self-demodulate in the far field. The resulting audio wave is proportional to the double time-derivative of the square of the modulation envelope. This thesis presents a fully analog processor which encodes the audio into two Pulse Width Modulated (PWM) signals in quadrature phase and sums them together to produce a Single Sideband (SSB) spectrum around the fundamental frequency of the PWM signals. The two signals are modulated between …

Experimental Study And Modeling Of The Gm-I Dependence Of Long-Channel Mosfets, Michael Fong Cheng

Master's Theses

This thesis describes an experimental study and modeling of the current-transconductance dependence of the ALD1106, ALD1107, and CD4007 arrays. The study tests the hypothesis that the I-gm dependence of these 7.8 µm to 10 µm MOSFETs conforms to the Advanced Compact Model (ACM). Results from performed measurements, however, do not support this expectation. Despite the relatively large length, both ALD1106 and ALD1107 show sufficiently pronounced ‘short-channel’ effects to render the ACM inadequate. As a byproduct of this effort, we confirmed the modified ACM equation. With an m factor of approximately 0.6, it captures the I-gm dependence with sub-28% maximum error …

Design, Analysis, And Simulation Of A Jitter Reduction Circuit (Jrc) System At 1ghz, Run Bin Yu

Master's Theses

The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the clock edge, could undermine the overall performance or even cause failures on the system. Deterministic jitter could be reduced during the designing process however random jitter during operation is somehow less-controllable and unavoidable. Being able to remove jitter on the clock would therefore play a vital role in system performance improvement.

This thesis implements a 1GHz fully feedforward jitter reduction circuit (JRC) which can be used as an on-chip IP core at clock tree terminals to …

Design Of An Integrated Acceleration Acquisition Subsystem To Satisfy High-Speed And Low-Area Requirements For Cubesats, Ryan J. Rumsey

Master's Theses

Cal Poly San Luis Obispo’s PolySat team is designing the Multipurpose Orbital Spring Ejection System (MOSES) in order to record acceleration data during the launch of CubeSats as well as to provide GPS coordinates to locate the position of CubeSats once they are injected into orbit. This work focuses on the design and development of the acceleration data acquisition (DAQ) subsystem of MOSES. This subsystem is designed around the need for a high-speed sampling system of at least 200 kHz across four channels of data, plus low-area limitations in the MOSES form factor which is roughly half the size of …

Oceanographic Instrument Simulator, Amy Chen

Master's Theses

The Monterey Bay Aquarium Research Institute (MBARI) established the Free Ocean Carbon Enrichment (FOCE) experiment to study the long-term effects of decreased ocean pH levels by developing in-situ platforms [1]. Deep FOCE (dpFOCE) was the first platform, which was deployed in 950 meters of water in Monterey Bay. After the conclusion of dpFOCE, MBARI developed an open source shallow water FOCE (swFOCE) platform located at around 250 meter of water to facilitate worldwide shallow water experiments on FOCE [1][2]. A shallow water platform can be more ubiquitous than a deep-water platform as shallow water instruments are less expensive (as it …

Design And Fabrication Techniques Of Devices For Embedded Power Active Contact Lens, Errol Heradio Leon

Master's Theses

This thesis designed and fabricated various devices that were interfaced to an IC for an active contact lens that notifies the user of an event by detection of an external wireless signal. The contact lens consisted of an embedded antenna providing communication with a 2.4GHz system, as well as inductive charging at an operating frequency of 13.56 MHz. The lens utilized a CBC005 5µAh thin film battery by Cymbet and a manufactured graphene super capacitor as a power source. The custom integrated circuit (IC) was designed using the On Semiconductor CMOS C5 0.6 µm process to manage …

Mos Current Mode Logic (Mcml) Analysis For Quiet Digital Circuitry And Creation Of A Standard Cell Library For Reducing The Development Time Of Mixed Signal Chips, David Marusiak

Master's Theses

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with …

The Bicycle-Powered Smartphone Charger, Chris Arntzen

Master's Theses

This thesis entails the design and fabrication of a smartphone charger that is powered by a bicycle dynamo hub. In addition to the design and validation of the charger prototype, this thesis involves the testing and characterization of the dynamo hub power source, the design and construction of specialized test equipment, and the design and prototyping of a handlebar-mounted case for the smartphone and charging electronics. With the intention of making the device a commercial product, price, aesthetics, and marketability are of importance to the design. An appropriate description of the charger circuit is a microcontroller-based energy management system, tailored …

Smart Wall Plug Design For The Dc House Project, Edward Constant Sibal

Master's Theses

The DC House project at Cal Poly State University faces a challenge of supplying DC voltage to household appliances. Each appliance in the DC House constitutes a DC load that has a unique voltage and power rating, hence the need to develop a smart DC wall plug that will automatically adjust to the operating voltage required by any DC load. This thesis entails a proof of concept design of the smart DC wall plug which can automatically detect an appliance’s voltage rating. The design employs a dc-dc converter in conjunction with a microcontroller to sense load current to properly adjust …

Linear Power-Efficient Rf Amplifier With Partial Positive Feedback, Matthew E. King

Master's Theses

Over the last decade, the number of mobile wireless devices on the market has increased substantially. New “multi-carrier” modulation schemes, such as OFDM, WCDMA, and WiMAX, have been developed to accommodate the increasing number of wireless subscribers and the demand for faster data rates within the limited commercial frequency spectrum. These complex modulation schemes create signals with high peak-to-average power ratios (PAPR), exhibiting rapid changes in the signal magnitude. To accommodate these high-PAPR signals, RF power amplifiers in mobile devices must operate under backed-off gain conditions, resulting in poor power efficiency. Various efficiency-enhancement solutions have been realized for backed-off devices …

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …