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Systems and Communications

2010

Articles 1 - 12 of 12

Full-Text Articles in Electronic Devices and Semiconductor Manufacturing

Design And Modeling Of A 40w Microwave Switch In Qfn 2x2 Package, Chin-Leong Lim Nov 2010

Design And Modeling Of A 40w Microwave Switch In Qfn 2x2 Package, Chin-Leong Lim

Chin-Leong Lim

This paper describes a Quad Flat Non-lead (QFN 2x2) packaged PIN diode switch that is capable of handling Continuous Wave (CW) power up to 40W and WCDMA signal up to 10W. The target application is the Transmit arm of a Transmit Receive switch for cellular base-stations. The part was developed in response to this market segment's aggressive cost-cutting pressure. Prior designs relied on more expensive ceramic packages.

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Lna Based On A Low Cost (~Usd1.30) Commercial Gaas Phemt Mmic Offers Wideband (0.4~1.4 Ghz) And Room-Temperature Low Noise (~0.3 Db) Performances That Satisfy The Ska Low Cost And No-Cooling Requirement, Chin-Leong Lim Aug 2010

Lna Based On A Low Cost (~Usd1.30) Commercial Gaas Phemt Mmic Offers Wideband (0.4~1.4 Ghz) And Room-Temperature Low Noise (~0.3 Db) Performances That Satisfy The Ska Low Cost And No-Cooling Requirement, Chin-Leong Lim

Chin-Leong Lim

Introduction: New generations of radio telescopes such as the Square Kilometre Array consist of millions of receivers scattered over a continent. The array’s quantity and geographic considerations ruled out the traditional radio astronomy LNA implementation; i.e. costly InP devices cooled by high-maintenance closed-cycle helium (He) refrigerators. Several LNA designs have been proposed to address the cost and room-temperature operation constraints but none appear a clear winner. Peltier and package-scale cooling have also been proposed as a lower cost/maintenance alternative to He cooling but when multiplied by the quantity required can still carve a significant chunk of the budget. Additionally, cooling …

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Wideband Limiter Fits Sot-323 Pack, Chin-Leong Lim Jun 2010

Wideband Limiter Fits Sot-323 Pack, Chin-Leong Lim

Chin-Leong Lim

Limiters protect wireless receiver front-ends from damage due to signal overload. The Schottky-PIN limiter is more protective than the self-biased PIN limiter because the former's limiting threshold is ~10 dB lower. Present implementation of the Schottky-PIN limiter use separate PIN and Schottky diodes. Additionally, some prior knowledge is necessary to select the correct PIN and Schottky diodes for limiter service. To miniaturize the limiter and to simplify the diode selection process, we combined a pair of limiter-optimized PIN and Schottky diodes into a compact and low-cost SOT-323 package. This paper describes the design, fabrication and experimental validation of the industry's …

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Negative Conductance Load Modulation Rf Power Amplifier, Cody R. Neslen Jun 2010

Negative Conductance Load Modulation Rf Power Amplifier, Cody R. Neslen

Master's Theses

The number of mobile wireless devices on the market has increased substantially over the last decade. The frequency spectrum has become crowded due to the number of devices demanding radio traffic and new modulation schemes have been developed to accommodate the number of users. These new modulation schemes have caused very poor efficiencies in power amplifiers for wireless transmission systems due to high peak-to-average power ratios (PAPR). This thesis first presents the issue with classical power amplifiers in modern modulation systems. A brief overview of current attempts to mitigate this issue is provided. A new RF power amplifier topology is …

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Pin Switch Protects Lna From Overloads, Chin-Leong Lim Mar 2010

Pin Switch Protects Lna From Overloads, Chin-Leong Lim

Chin-Leong Lim

The objective of this paper is to describe how a Microwave Monolithic Integrated Circuit (MMIC) can be paired with an external PIN diode bypass switch in the implementation of a Low Noise Amplifier (LNA) with overload protection feature for mobile TV receiver applications. In the preliminary phase of the design, competing schemes for reducing LNA gain were reviewed and their respective cost-performance trade-offs were benchmarked against the customer’s set of requirements. Based on the selected design, a “proof of concept” prototype was then assembled and tested. The key components of this switch by-passable LNA were sourced from in-house product portfolio, …

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Lna With A Bypass Mode Improves Overload Resistance For Mobile Tv, Chin-Leong Lim Mar 2010

Lna With A Bypass Mode Improves Overload Resistance For Mobile Tv, Chin-Leong Lim

Chin-Leong Lim

Objective: This paper describes how a Microwave Monolithic Integrated Circuit (MMIC) can be paired with an external PIN diode bypass switch in the implementation of a Low Noise Amplifier (LNA) with overload protection feature for mobile TV receiver applications.

Method: In the preliminary phase of the design, competing schemes for reducing LNA gain were reviewed and their respective cost-performance trade-offs were benchmarked against the customer’s set of requirements. Based on the selected design, a “proof of concept” prototype was then assembled and tested.

Material: The key components of this switch by-passable LNA were sourced from in-house product portfolio, consisting of …

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Super-High-Frequency Two-Port Aln Contour-Mode Resonators For Rf Applications, Matteo Rinaldi, Chiara Zuniga, Chengjie Zuo, Gianluca Piazza Dec 2009

Super-High-Frequency Two-Port Aln Contour-Mode Resonators For Rf Applications, Matteo Rinaldi, Chiara Zuniga, Chengjie Zuo, Gianluca Piazza

Matteo Rinaldi

This paper reports on the design and experimental verification of a new class of thin-film (250 nm) super-high-frequency laterally-vibrating piezoelectric microelectromechanical (MEMS) resonators suitable for the fabrication of narrow-band MEMS filters operating at frequencies above 3 GHz. The device dimensions have been opportunely scaled both in the lateral and vertical dimensions to excite a contour-extensional mode of vibration in nanofeatures of an ultra-thin (250 nm) AlN film. In this first demonstration, 2-port resonators vibrating up to 4.5 GHz have been fabricated on the same die and attained electromechanical coupling, kt2, in excess of 1.5%. These devices are employed to synthesize …

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The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh Dec 2009

The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh

Dr. Rozita Teymourzadeh, CEng.

Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the …

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Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh Dec 2009

Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation …

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Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R Dec 2009

Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R

Dr. Rozita Teymourzadeh, CEng.

The photovoltaic system uses the photovoltaic array as a source of electrical power for the direct conversion of the sun’s radiation to direct current without any environmental hazards. The main purpose of this research is to design of a converter with Maximum Power Point Tracker (MPPT) algorithm for any typical application of soil humidity control. Using this setup the major energy from the solar panel is used for the control of soil humidity. The design of the converter with MPPT together with the soil humidity control logic is presented in this paper. Experimental testing of the design controller is implemented …

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On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh Dec 2009

On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was …

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On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman Dec 2009

On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report …

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