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On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh
On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh
Dr. Rozita Teymourzadeh, CEng.
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was …