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Computer and Systems Architecture Commons™
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Articles 1 - 13 of 13
Full-Text Articles in Computer and Systems Architecture
Developing A Miniature Smart Boat For Marine Research, Michael Isaac Eirinberg
Developing A Miniature Smart Boat For Marine Research, Michael Isaac Eirinberg
Computer Engineering
This project examines the development of a smart boat which could serve as a possible marine research apparatus. The smart boat consists of a miniature vessel containing a low-cost microcontroller to live stream a camera feed, GPS telemetry, and compass data through its own WiFi access point. The smart boat also has the potential for autonomous navigation. My project captivated the interest of several members of California Polytechnic State University, San Luis Obispo’s (Cal Poly SLO) Marine Science Department faculty, who proposed a variety of fascinating and valuable smart boat applications.
Extension Of Cpe 454 Operating System, Joseph Nathaniel Arhar
Extension Of Cpe 454 Operating System, Joseph Nathaniel Arhar
Computer Science and Software Engineering
This project extended on the operating system I wrote in CPE 454 by adding additional features on top of the existing implementation. In order to implement them, I researched operating system design patterns and hardware details. I used wiki.osdev.org for most research, just like I did in CPE 454. The source code for the project is at https://github.com/josepharhar/jos.
Iota Pi Application For Ios, Deborah Newberry
Iota Pi Application For Ios, Deborah Newberry
Computer Science and Software Engineering
Kappa Kappa Psi is a national honorary fraternity for college band members. They meet every Sunday night, and during these meetings they plan events (both internal and external) that aim to meet our goal of making sure that the Cal Poly band programs have their social, financial, material, and educational needs satisfied. This paper details the steps I took to create an application for them to use internally to help ease organizational processes.
Android Drone: Remote Quadcopter Control With A Phone, Aubrey John Russell
Android Drone: Remote Quadcopter Control With A Phone, Aubrey John Russell
Computer Engineering
The purpose of the “Android Drone” project was to create a quadcopter that can be controlled by user input sent over the phone’s Wi-Fi connection or 4G internet connection. Furthermore, the purpose was also to be able to receive live video feedback over the internet connection, thus making the drone an inexpensive option compared to other, equivalent drones that might cost thousands of dollars. Not only that, but the Android phone also has a host of other useful features that could be utilized by the drone: this includes GPS, pathing, picture taking, data storage, networking and TCP/IP, a Java software …
Design Of Cpu Simulation Software For Armv7 Instruction Set Architecture, Dillon Tellier
Design Of Cpu Simulation Software For Armv7 Instruction Set Architecture, Dillon Tellier
Computer Engineering
Simulations have long been a part of the engineering process in both the professional and academic domain. From a pedagogic standpoint, simulations allow students to explore the dynamics of engineering scenarios by controlling variables, taking measurements, and observing behavior which would be difficult or impossible without simulation. One such tool is a CPU simulator used in Cal Poly’s Computer Architecture classes; this software simulates an instruction accurate operation of a computer processor and reports statistics regarding the execution of the supplied compiled machine code. For the last several years Cal Poly’s computer architecture classes have used a previous version of …
Regen: Optimizing Genetic Selection Algorithms For Heterogeneous Computing, Scott Kenneth Swinkleb Winkleblack
Regen: Optimizing Genetic Selection Algorithms For Heterogeneous Computing, Scott Kenneth Swinkleb Winkleblack
Master's Theses
GenSel is a genetic selection analysis tool used to determine which genetic markers are informational for a given trait. Performing genetic selection related analyses is a time consuming and computationally expensive task. Due to an expected increase in the number of genotyped individuals, analysis times will increase dramatically. Therefore, optimization efforts must be made to keep analysis times reasonable.
This thesis focuses on optimizing one of GenSel’s underlying algorithms for heterogeneous computing. The resulting algorithm exposes task-level parallelism and data-level parallelism present but inaccessible in the original algorithm. The heterogeneous computing solution, ReGen, outperforms the optimized CPU implementation achieving a …
Virtual Reality Engine Development, Varun Varahamurthy
Virtual Reality Engine Development, Varun Varahamurthy
Master's Theses
With the advent of modern graphics and computing hardware and cheaper sensor and display technologies, virtual reality is becoming increasingly popular in the fields of gaming, therapy, training and visualization. Earlier attempts at popularizing VR technology were plagued by issues of cost, portability and marketability to the general public. Modern screen technologies make it possible to produce cheap, light head-mounted displays (HMDs) like the Oculus Rift, and modern GPUs make it possible to create and deliver a seamless real-time 3D experience to the user. 3D sensing has found an application in virtual and augmented reality as well, allowing for a …
Cuda Web Api Remote Execution Of Cuda Kernels Using Web Services, Massimo J. Becker
Cuda Web Api Remote Execution Of Cuda Kernels Using Web Services, Massimo J. Becker
Master's Theses
Massively parallel programming is an increasingly growing field with the recent introduction of general purpose GPU computing. Modern graphics processors from NVIDIA and AMD have massively parallel architectures that can be used for such applications as 3D rendering, financial analysis, physics simulations, and biomedical analysis. These massively parallel systems are exposed to programmers through in- terfaces such as NVIDIAs CUDA, OpenCL, and Microsofts C++ AMP. These frame- works expose functionality using primarily either C or C++. In order to use these massively parallel frameworks, programs being implemented must be run on machines equipped with massively parallel hardware. These requirements limit …
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Master's Theses
The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …
Max Flow Spill Code Placement Algorithm Implemented In Gcc 4.4.3, Stephen Robert Beard
Max Flow Spill Code Placement Algorithm Implemented In Gcc 4.4.3, Stephen Robert Beard
Computer Engineering
The placement of spill code plays an important role in the register allocator of an optimizing compiler. Many computer architectures possess a register linkage convention that dictates which registers are preserved across function calls and which are not. This project addresses the problem of optimizing spill code that is associated with register linkage conventions.
This algorithm was created by Dr. Chris Lupo and is described in the paper Beyond Register Allocation: a Novel Algorithm for Spill-Code Placement. The algorithm was implemented for GCC 2.5.7 for a PA-RISC architecture [4]. The work in this project will involve porting the existing code …
Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci
Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci
Computer Engineering
Digital media players often include a visualization component that allows a user to watch a visualization synchronized to their music or videos. This project uses the visualization plugin API of an existing media playback program (WinAmp) but it displays its visuals using physical LED lights. Instead of outputting visuals to the computer screen, data is sent over USB to a micro controller that runs the LED lights. This project aims to give users a more visceral visual experience than traditional visualizations on the computer screen.
A Neural Network Approach To Border Gateway Protocol Peer Failure Detection And Prediction, Cory B. White
A Neural Network Approach To Border Gateway Protocol Peer Failure Detection And Prediction, Cory B. White
Master's Theses
The size and speed of computer networks continue to expand at a rapid pace, as do the corresponding errors, failures, and faults inherent within such extensive networks. This thesis introduces a novel approach to interface Border Gateway Protocol (BGP) computer networks with neural networks to learn the precursor connectivity patterns that emerge prior to a node failure. Details of the design and construction of a framework that utilizes neural networks to learn and monitor BGP connection states as a means of detecting and predicting BGP peer node failure are presented. Moreover, this framework is used to monitor a BGP network …
Post Register Allocation Spill Code Optimization, Christopher Lupo, Kent Wilken
Post Register Allocation Spill Code Optimization, Christopher Lupo, Kent Wilken
Computer Science and Software Engineering
A highly optimized register allocator should provide an efficient placement of save/restore code for procedures that contain calls. This paper presents a new approach to placing callee-saved save and restore instructions that generalizes Chow's shrink-wrapping technique (Chow 1988). An efficient, profile-guided, hierarchical spill code placement algorithm is used to analyze the structure of a procedure to calculate the minimum dynamic execution count locations to place callee-saved save and restore code. The algorithm is implemented in the Gnu Compiler Collection and has been tested on the SPEC CPU2000 Integer Benchmark suite. Results show that the technique reduces the number of dynamic …