Computer Engineering Commons^™

Design Of Area-Efficient Iir Filter Using Fppe, Ramyarani Nallathambi, Subbiah Veerana, Deepa Prabhakaran

Turkish Journal of Electrical Engineering and Computer Sciences

Floating point arithmetic circuits provide wide dynamic range and high precision, and they are widely used in scientific computing and signal processing applications, but the complexity increases in hardware implementations of floating point units. In VLSI design architecture, many applications suffer in size of the components used in logical operations. The aim of reducing architecture is to gain reduction in power loss and also in area, but the reduction in size of the components leads to an increase in delay and memory. Hence, to overcome these limitations and to optimize the area, a novel design of floating point processing element …

Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally

Information Science Faculty Publications

One of the most important Internet of Things applications is the wireless body sensor network (WBSN), which can provide universal health care, disease prevention, and control. Due to large deployments of small scale smart sensors in WBSNs, security, and privacy guarantees (e.g., security and safety-critical data, sensitive private information) are becoming a challenging issue because these sensor nodes communicate using an open channel, i.e., Internet. We implement data integrity (to resist against malicious tampering) using the secure hash algorithm 3 (SHA-3) when smart sensors in WBSNs communicate with each other using the Internet. Due to the limited resources (i.e., storage, …

H.264 Video Decoder Implemented On Fpgas Using 3×3 And 2×2 Networks-On-Chip, Ian Barge, Cristinel Ababei

Electrical and Computer Engineering Faculty Research and Publications

In this paper, we present the design and verification of the H.264 video decoder algorithm on FPGAs. The primary difference compared to previously reported designs is that the communication between the decoder modules is done via a network-on-chip in our case. The proposed design is a complete system level hardware design described in VHDL and Verilog. We report experimental results for two different implementations. The first implementation uses a 3×3 network-on-chip and is validated on the DE4 development board, which uses Altera's Stratix IV GX FPGA chip. The second implementation uses a 2×2 network-on-chip and is validated on the Cyclone …

An Efficient And Cost Effective Fpga Based Implementation Of The Viola-Jones Face Detection Algorithm, Peter Irgens, Curtis Bader, Theresa Lé, Devansh Saxena, Cristinel Ababei

Electrical and Computer Engineering Faculty Research and Publications

We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and …

Performance Analysis And Optimization Of Cluster-Based Mesh Fpga Architectures: Design Methodology And Cad Tool Support, Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez

Turkish Journal of Electrical Engineering and Computer Sciences

Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design's big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental method and benchmarks circuit implementation, this work provides a detailed exploration and analyses of the effect of cluster functionality on the proposed cluster-based FPGA in terms of power dissipation, area density, and delay. The exploration results showed that architecture with high cluster size provides high speed …

Novel Dynamic Partial Reconfiguration Implementations Of The Support Vector Machine Classifier On Fpga, Hanaa Hussain, Khaled Benkrid, Hüseyi̇n Şeker

Turkish Journal of Electrical Engineering and Computer Sciences

The support vector machine (SVM) is one of the highly powerful classifiers that have been shown to be capable of dealing with high-dimensional data. However, its complexity increases requirements of computational power. Recent technologies including the postgenome data of high-dimensional nature add further complexity to the construction of SVM classifiers. In order to overcome this problem, hardware implementations of the SVM classifier have been proposed to benefit from parallelism to accelerate the SVM. On the other hand, those implementations offer limited flexibility in terms of changing parameters and require the reconfiguration of the whole device. The latter interrupts the operation …

Performance Evaluation Of A New Efficient H.264 Intraprediction Scheme, Sara Hamdy, Mostafa Ibrahim, Mohamed Osman

Turkish Journal of Electrical Engineering and Computer Sciences

The paper presents a new efficient H.264/AVC$ 4 \times 4$ intraprediction scheme. The new prediction scheme is based on the best prediction matrix mode. The main idea behind the new prediction scheme is to combine the most usable intraprediction modes, {vertical - horizontal - DC} , into a new efficient prediction mode. The new prediction scheme is implemented using VHDL and hence it uses the full advantages of inherent parallelism in the hardware. We evaluate the performance of this prediction scheme in terms of compression ratio, peak signal to noise ratio, and bit rate using seven video sequences. Moreover, we …

Adaptive Controller Using Runtime Partial Hardware Reconfiguration For Unmanned Aerial Vehicles (Uavs), Nikhil Thomas

Graduate Theses and Dissertations

The goal of this thesis is to explore the feasibility of a multirotor controller system which can dynamically change the arm configuration of a multirotor. Currently most of the multirotor systems have to be powered down, rewired, and programmed with new firmware, to configure how many arms/motors they use to fly. The focus of our effort is to develop a Field Programmable Gate Array (FPGA) based hardware/software controller which uses dynamic partial hardware reconfiguration to switch the arm/motor configuration of a multirotor during operation. We believe that this will make a multirotor more fault tolerant and adaptive. This thesis explains …

Design And Verification Environment For High-Performance Video-Based Embedded Systems, Michael Mefenza Nentedem

Graduate Theses and Dissertations

In this dissertation, a method and a tool to enable design and verification of computation demanding embedded vision-based systems is presented. Starting with an executable specification in OpenCV, we provide subsequent refinements and verification down to a system-on-chip prototype into an FPGA-Based smart camera. At each level of abstraction, properties of image processing applications are used along with structure composition to provide a generic architecture that can be automatically verified and mapped to the lower abstraction level. The result is a framework that encapsulates the computer vision library OpenCV at the highest level, integrates Accelera's System-C/TLM with UVM and QEMU-OS …

Fpga Accelerated Discrete-Surf For Real-Time Homography Estimation, Andrew C. Leighner

Theses and Dissertations

This paper describes our hardware accelerated, FPGA implementation of SURF, named Discrete SURF, to support real-time homography estimation for close range aerial navigation. The SURF algorithm provides feature matches between a model and a scene which can be used to find the transformation between the camera and the model. Previous implementations of SURF have partially employed FPGAs to accelerate the feature detection stage of upright only image comparisons. We extend the work of previous implementations by providing an FPGA implementation that allows rotation during image comparisons in order to facilitate aerial navigation. We also expand beyond feature detection as the …

A Comparative Study Of Two Different Fpga-Based Arrhythmia Classifier Architectures, Ahmet Turan Özdemi̇r, Kenan Danişman

Turkish Journal of Electrical Engineering and Computer Sciences

Early diagnosis of dangerous heart conditions is very important for the treatment of heart diseases and for the prevention of sudden cardiac death. Automatic electrocardiogram (ECG) arrhythmia classifiers are essential to timely diagnosis. However, most of the medical diagnosis systems proposed in the literature are software-based. This work focused on the hardware implementation of a mobile artificial neural network (ANN)-based arrhythmia classifier that is implemented on a field programmable gate array (FPGA) as a single chip solution, as an alternative to various software models of ANNs. Due to the parallel nature of ANNs, hardware implementation of ANNs needs a large …

Co-Emulation Of Scan-Chain Based Designs Utilizing Sce-Mi Infrastructure, Bill Jason Pidlaoan Tomas

UNLV Theses, Dissertations, Professional Papers, and Capstones

Simulation times of complex System-on-Chips (SoC) have grown exponentially as designs reach the multi-million ASIC gate range. Verification teams have adopted emulation as a prominent methodology, incorporating high-level testbenches and FPGA/ASIC hardware for system-level testing (SLT). In addition to SLT, emulation enables software teams to incorporate software applications with cycle-accurate hardware early on in the design cycle. The Standard for Co-Emulation Modeling Interface (SCE-MI) developed by the Accelera Initiative, is a widely used communication protocol for emulation which has been accepted by major electronic design automation (EDA) companies.

Scan-chain is a design-for-test (DFT) methodology used for testing digital circuits. To …

Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa

UNLV Theses, Dissertations, Professional Papers, and Capstones

Differential equations play a significant role in many disciplines of science and engineering. Solving and implementing Ordinary Differential Equations (ODEs) and partial Differential Equations (PDEs) effectively are very essential as most complex dynamic systems are modeled based on these equations. High Performance Computing (HPC) methodologies are required to compute and implement complex and data intensive applications modeled by differential equations at higher speed. There are, however, some challenges and limitations in implementing dynamic system, modeled by non-linear ordinary differential equations, on digital hardware. Modeling an integrator involves data approximation which results in accuracy error if data values are not considered …

A Parameterized Stereo Vision Core For Fpgas, Mark Chang, Stephen Longfield

Mark L. Chang

We present a parameterized stereo vision core suitable for a wide range of FPGA targets and stereo vision applications. By enabling easy tuning of algorithm parameters, our system allows for rapid exploration of the design space and simpler implementation of high-performance stereo vision systems. This implementation utilizes the census transform algorithm to calculate depth information from a pair of images delivered from a simulated stereo camera pair. This work advances our previous work through implementation improvements, a stereo camera pair simulation framework, and a scalable stereo vision core.

An Adaptive Modular Redundancy Technique To Self-Regulate Availability, Area, And Energy Consumption In Mission-Critical Applications, Rawad N. Al-Haddad

Electronic Theses and Dissertations

As reconfigurable devices' capacities and the complexity of applications that use them increase, the need for self-reliance of deployed systems becomes increasingly prominent. A Sustainable Modular Adaptive Redundancy Technique (SMART) composed of a dual-layered organic system is proposed, analyzed, implemented, and experimentally evaluated. SMART relies upon a variety of self-regulating properties to control availability, energy consumption, and area used, in dynamically-changing environments that require high degree of adaptation. The hardware layer is implemented on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach called a Reconfigurable Adaptive Redundancy System (RARS). The software layer supervises …

Fully Parallel Ann-Based Arrhythmia Classifier On A Single-Chip Fpga: Fpaac, Ahmet Turan Özdemi̇r, Kenan Danişman

Turkish Journal of Electrical Engineering and Computer Sciences

Recognition of cardiac arrhythmias by electrocardiogram (ECG) is an important issue for diagnosis of cardiac abnormalities. Many studies on recognition of cardiac arrhythmias by ECG, using various techniques, have been performed in the past 20 years. Artificial neural networks (ANNs) are the most widely used tool in medical diagnosis systems (MDS) because of their powerful prediction characteristics. An ANN model is inspired by real biological neural networks, with a parallel structure that is potentially fast for computation. However, the suggested ANN architectures in the literature can only be run sequentially, on powerful processors, due to their complexity. Our approach enables …

Reconode: Towards An Autonomous Multi-Robot Team Agent For Usar, Kang Li

Electronic Theses and Dissertations

Urban search and rescue (USAR) robots can benefit from small size as it facilitates movement in cramped quarters. Yet, small size limits actuator power, sensor payloads, computational capacity and battery life. We are alleviating these issues by developing the hardware and software infrastructure for high performance, heterogeneous, dynamically-reconfigurable miniature USAR robots, as well as a host of other relevant applications. In this thesis, a generic modular embedded system architecture based on the RecoNode multiprocessor is proposed, which consists of a set of hardware and software modules that can be configured to construct various types of robot systems for dynamic and …

Real Time Fault Detection And Diagnostics Using Fpga-Based Architecture, Nathan P. Naber

Theses and Dissertations

Errors within circuits caused by radiation continue to be an important concern to developers. A new methodology of real time fault detection and diagnostics utilizing FPGA based architectures while under radiation were investigated in this research. The contributions of this research are focused on three areas; a full test platform to evaluate a circuit while under irradiation, an algorithm to detect and diagnose fault locations within a circuit, and finally to characterize Triple Design Triple Modular Redundancy (TDTMR), a new form of TMR. Five different test setups, injected fault test, gamma radiation test, thermal radiation test, optical laser test, and …

An Fpga-Based System For Tracking Digital Information Transmitted Via Peer-To-Peer Protocols, Karl R. Schrader, Barry E. Mullins, Gilbert L. Peterson, Robert F. Mills

Faculty Publications

This paper presents a Field Programmable Gate Array (FPGA)-based tool designed to process file transfers using the BitTorrent Peer-to-Peer (P2P) protocol and VoIP phone calls made using the Session Initiation Protocol (SIP). The tool searches selected control messages in real time and compares the unique identifier of the shared file or phone number against a list of known contraband files or phone numbers. Results show the FPGA tool processes P2P packets of interest 92% faster than a software-only configuration and is 97.6% accurate at capturing and processing messages at a traffic load of 89.6 Mbps.

High-Performance Heterogeneous Computing With The Convey Hc-1, Jason D. Bakos

Faculty Publications

Unlike other socket-based reconfigurable coprocessors, the Convey HC-1 contains nearly 40 field-programmable gate arrays, scatter-gather memory modules, a high-capacity crossbar switch, and a fully coherent memory system.

A Special-Purpose Architecture For Solving The Breakpoint Median Problem, Jason D. Bakos, Panormitis E. Elenis

Faculty Publications

In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our hardware breakpoint median achieves a maximum speedup of 1005times over software. When the coprocessor is used to accelerate the entire reconstruction procedure, we achieve a maximum application speedup of 417times. The results in this paper suggest that FPGA-based acceleration is a promising approach for computationally expensive phylogenetic problems, in spite of the fact that the involved algorithms are based …

Significance Of Logic Synthesis In Fpga-Based Design Of Image And Signal Processing Systems, Mariusz Rawski, Henry Selvaraj, Bogdan J. Falkowski, Tadeusz Luba

Electrical & Computer Engineering Faculty Research

This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, general-purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally, …

Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley

Theses and Dissertations

There is a need to expedite the process of designing military hardware to stay ahead of the adversary. The core of this project was to build reusable, synthesizeable libraries to make this a possibility. In order to build these libraries, Matlab® commands and functions, such as Conv2, Round, Floor, Pinv, etc., had to be converted into reusable VHDL modules. These modules make up reusable libraries for the Mission Specific Process (MSP) which will support AFRL/RY. The MSP allows the VLSI design process to be completed in a mere matter of days or months using an FPGA or ASIC design, as …

Fpga Acceleration Of Gene Rearrangement Analysis, Jason D. Bakos

Faculty Publications

In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and comparative genomics. In our initial study, we have targeted a specific application that reconstructs maximum-parsimony (MP) phylogenies for gene-rearrangement data. Like other prevalent applications in computational biology, this application relies on a control-dependent, memory-intensive, and non-arithmetic combinatorial optimization algorithm. To achieve hardware acceleration, we developed an FPGA core design that implements the application's primary bottleneck computation. Because our core is lightweight, we are able to synthesize multiple cores on a single FPGA. …

Exploring Hardware Based Primitives To Enhance Parallel Security Monitoring In A Novel Computing Architecture, Stephen D. Mott

Theses and Dissertations

This research explores how hardware-based primitives can be implemented to perform security-related monitoring in real-time, offer better security, and increase performance compared to software-based approaches. In doing this, we propose a novel computing architecture, derived from a contemporary shared memory architecture, that facilitates efficient security-related monitoring in real-time, while keeping the monitoring hardware itself safe from attack. This architecture is flexible, allowing security to be tailored based on the needs of the system. We have developed a number of hardware-based primitives that fit into this architecture to provide a wide array of monitoring capabilities. A number of these primitives provide …

Evolvable Reconfigurable Hardware Framework For Edge Detection, Nader I. Rafla

Electrical and Computer Engineering Faculty Publications and Presentations

Systems on Reconfigurable Chips contain rich resources of logic, memory, and processor cores on the same fabric. This platform is suitable for implementation of Evolvable Reconfigurable Hardware Architectures (ERHA). It is based on the idea of combining reconfigurable Field Programmable Gate Arrays (FPGA) along with genetic algorithms (GA) to perform the reconfiguration operation. This architecture is a suitable candidate for implementation of early-processing stage operators of image processing such as filtering and edge detection. However, there are still fundamental issues need to be solved regarding the on-chip reprogramming of the logic. This paper presents a framework for implementing an evolvable …

A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism, Charles L. Cathey, Jason D. Bakos, Duncan A. Buell

Faculty Publications

This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This architecture is based on multiple FPGAs organized in a scalable direct network that is substantially more interconnect-efficient than currently used crossbar technology. In addition, we discuss several ancillary issues and propose solutions required to support this architecture and achieve maximal performance for general-purpose applications; these include supporting IP, mapping techniques, and routing policies that enable greater flexibility for architectural evolution and code portability.

Evaluation Of A Field Programmable Gate Array Circuit Reconfiguration System, Jason L. Ives

Theses and Dissertations

This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. …

Real-Time 3d Image Visualization System For Digital Video On A Single Chip, Nader I. Rafla

Electrical and Computer Engineering Faculty Publications and Presentations

Implementation of a real-time image visualization system on a reconfigurable chip (FPGA) is proposed. The system utilizes an innovative stereoscopic image capture, processing and visualization technique. Implementation is done as a two stage process. In the first stage, the stereo pair is captured using two image sensors. The captured images are then synchronized and sent to the second stage for fusion. A controller module is developed, designed, and placed on the FPGA for this purpose. The second stage is used for reconstruction and visualization of the 3D image. An innovative technique employing dual-processor architecture on the same single FPGA is …

Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar

Electrical & Computer Engineering Faculty Research

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder.