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Articles 1 - 6 of 6
Full-Text Articles in Computer Engineering
An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri
An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri
Masters Theses
Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …
Design Of An Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture, Joshua R. Templin
Design Of An Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture, Joshua R. Templin
All Graduate Theses and Dissertations, Spring 1920 to Summer 2023
Processing power is a key technical challenge holding back the development of a high-performance software defined radio (SDR). Traditionally, SDR has utilized digital signal processors (DSPs), but increasingly complex algorithms, higher data rates, and multi-tasking needs have exceed the processing capabilities of modern DSPs. Reconfigurable computers, such as field-programmable gate arrays (FPGAs), are popular alternatives because of their performance gains over software for streaming data applications like SDR. However, FPGAs have not yet realized the ideal SDR because architectures have not fully utilized their partial reconfiguration (PR) capabilities to bring needed flexibility. A reconfigurable processor architecture is proposed that utilizes …
Accelerated Frame Data Relocation On Xilinx Field Programmable Gate Array, Ramachandra Kallam
Accelerated Frame Data Relocation On Xilinx Field Programmable Gate Array, Ramachandra Kallam
All Graduate Theses and Dissertations, Spring 1920 to Summer 2023
Emerging reconfiguration techniques that include partial dynamic reconfiguration and partial bitstream relocation have been addressed in the past in order to expose the flexibility of field programmable gate array at runtime. Partial bitstream relocation is a technique used to target a partial bitstream of a partial reconfigurable region (PRR) onto other identical reconfigurable regions inside an FPGA, while partial dynamic reconfiguration is used to target a single reconfigurable region. Prior works in this domain aim to minimize "relocation time" with the help of on-chip or on-line processing. In this thesis, a novel PRR-PRR relocation algorithm is proposed and implemented both …
Acceleration Of Biomolecular Simulations Using Fpga-Based Reconfigurable Computing, Ananth Nallamuthu
Acceleration Of Biomolecular Simulations Using Fpga-Based Reconfigurable Computing, Ananth Nallamuthu
All Theses
A paradigm shift is occurring in the way compute-intensive scientific applications are developed. Thanks to advancements in commercially viable hybrid architectures for High-Performance Computing (HPC), the focus has shifted from improving performance by merely scaling algorithms on von Neumann computing nodes to fully exploiting additional computational capabilities provided by accelerators such as FPGAs (Field Programmable Gate Arrays) and GPGPUs (General Purpose Graphical Processing Units).
Computational chemists use Molecular Dynamics (MD) simulations like LAMMPS (Large Scale Atomic Molecular Massively Parallel Systems) and NAMD (NAnoscale Molecular Dynamics) to simulate biomolecular behaviour such as protein folding and small molecule docking to proteins. MD …
Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski
Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski
Department of Electrical Engineering and Computer Science - Daytona Beach
This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented.
New Approach Fpga-Based Implementation Of Discontinuous Svpwm}, Tole Sutikno, Auzani Jidin, Nik Rumzi Nik Idris
New Approach Fpga-Based Implementation Of Discontinuous Svpwm}, Tole Sutikno, Auzani Jidin, Nik Rumzi Nik Idris
Turkish Journal of Electrical Engineering and Computer Sciences
The discontinuous space vector pulse-width modulation (DSVPWM) is a well-known technique offering lower switching losses than continuous SVPWM. At the same, average switching frequency, or a switching frequency 1.5 times higher than utilized in continuous SVPWM, the discontinuous SVPWM results in lower current harmonic distortions than that obtained in continuous SVPWM at high modulation indices. This paper is concerned with the design and realization of new FPGA approach based a 5-segment discontinuous SVPWM operated at 40 kHz switching frequency. It will be shown that the implementation of the discontinuous SVPWM utilized in FPGA, to execute some complex tasks, is simplified …