Open Access. Powered by Scholars. Published by Universities.®

Computer Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

FPGA

Discipline
Institution
Publication Year
Publication
Publication Type
File Type

Articles 1 - 30 of 60

Full-Text Articles in Computer Engineering

An Fpga Implementation Of Digital Guitar Effects, Carson James Robles Jun 2019

An Fpga Implementation Of Digital Guitar Effects, Carson James Robles

Computer Engineering

One of the most versatile aspects of the electric guitar is its ability to change its sound completely and on-the-fly through the use of effects pedals. Conventional guitar pedals contain one effect and can be chained together. The goal of this project is to serve as a contained multi-effects station with five popular electric guitar effects packed into one product. On top of this, the effects each have two tunable parameters to allow users to dial in the exact tone they are looking for. All of the signal processing done in this project is conducted on an FPGA which also ...


Analyzing Energy Savings In An Fpga Video Processing System Using Dynamic Partial Reconfiguration, Robert Cole Wernsman Jan 2019

Analyzing Energy Savings In An Fpga Video Processing System Using Dynamic Partial Reconfiguration, Robert Cole Wernsman

Graduate Theses and Dissertations

Dynamic Partial Reconfiguration (DPR) can be a useful tool for maximizing FPGA performance while minimizing power consumption and FPGA size requirements. This work explores the application of the DPR technique in a computer vision application that implements two different edge detection algorithms (FASTX and Sobel). This technique could allow for a similar computer vision system to be realized on a smaller, low-power chipset. Different algorithms can have unique characteristics that yield better performance in certain scenarios; the best algorithm for the current scenario may change during runtime. However, implementing all available algorithms in hardware increases the space and power requirements ...


Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally Jul 2018

Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally

Information Science Faculty Publications

One of the most important Internet of Things applications is the wireless body sensor network (WBSN), which can provide universal health care, disease prevention, and control. Due to large deployments of small scale smart sensors in WBSNs, security, and privacy guarantees (e.g., security and safety-critical data, sensitive private information) are becoming a challenging issue because these sensor nodes communicate using an open channel, i.e., Internet. We implement data integrity (to resist against malicious tampering) using the secure hash algorithm 3 (SHA-3) when smart sensors in WBSNs communicate with each other using the Internet. Due to the limited resources ...


A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar Jun 2018

A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar

Computer Engineering

This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in ...


Acceleration Of K-Nearest Neighbor And Srad Algorithms Using Intel Fpga Sdk For Opencl, Liyuan Liu Mar 2018

Acceleration Of K-Nearest Neighbor And Srad Algorithms Using Intel Fpga Sdk For Opencl, Liyuan Liu

Electronic Theses and Dissertations

Field Programmable Gate Arrays (FPGAs) have been widely used for accelerating machine learning algorithms. However, the high design cost and time for implementing FPGA-based accelerators using traditional HDL-based design methodologies has discouraged users from designing FPGA-based accelerators. In recent years, a new CAD tool called Intel FPGA SDK for OpenCL (IFSO) allowed fast and efficient design of FPGA-based hardware accelerators from high level specification such as OpenCL. Even software engineers with basic hardware design knowledge could design FPGA-based accelerators. In this thesis, IFSO has been used to explore acceleration of k-Nearest-Neighbour (kNN) algorithm and Speckle Reducing Anisotropic Diffusion (SRAD) simulation ...


Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey Mar 2018

Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey

Theses and Dissertations

The inflexible nature of traditional computer networks has led to tightly-integrated systems that are inherently difficult to manage and secure. New designs move low-level network control into software creating software-defined networks (SDN). Augmenting an existing network with these enhancements can be expensive and complex. This research investigates solutions to these problems. It is hypothesized that an add-on device, or "shim" could be used to make a traditional switch behave as an OpenFlow SDN switch while maintaining reasonable performance. A design prototype is found to cause approximately 1.5% reduction in throughput for one ow and less than double increase in ...


A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman Jan 2018

A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman

Theses and Dissertations

One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single ...


An Fpga-Based Hardware Accelerator For Iris Segmentation, Joseph Avey Jan 2018

An Fpga-Based Hardware Accelerator For Iris Segmentation, Joseph Avey

Graduate Theses and Dissertations

Biometric authentication is becoming an increasingly prevalent way to identify a person based on unique physical traits such as the fingerprint, the face, and/or the iris. The iris stands out particularly among these traits due to its relative invariability with time and high uniqueness. However, iris recognition without special, dedicated tools like near-infrared (NIR) cameras and stationary high-performance computers is a challenge. Solutions have been proposed to target mobile platforms like smart phones and tablets by making use of the RGB camera commonly found on those platforms. These solutions tend to be slower than the former due to the ...


Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young Aug 2017

Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young

Masters Theses

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the ...


Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart Aug 2017

Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart

Masters Theses

Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA ...


General-Purpose Digital Filter Platform, Michael Cheng Jun 2017

General-Purpose Digital Filter Platform, Michael Cheng

Electrical Engineering

This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes ...


A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah May 2017

A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah

Theses and Dissertations

The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables ...


Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge Apr 2017

Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge

Master's Theses (2009 -)

This thesis develops the first fully network-on-chip (NoC) based h.264 video decoder implemented in real hardware on a field programmable gate array (FPGA). This thesis starts with an overview of the h.264 video coding standard and an introduction to the NoC communication paradigm. Following this, a series of processing elements (PEs) are developed which implement the component algorithms making up the h.264 video decoder. These PEs, described primarily in VHDL with some Verilog and C, are then mapped to an NoC which is generated using the CONNECT NoC generation tool. To demonstrate the scalability of the proposed ...


Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding Jan 2017

Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding

Theses and Dissertations

With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.

In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs ...


Evaluation Of A Soc For Real-Time 3d Slam, Benjamin Williams Jan 2017

Evaluation Of A Soc For Real-Time 3d Slam, Benjamin Williams

Graduate Theses and Dissertations

SLAM, or Simultaneous Localization and Mapping, is the combined problem of constructing a map of an agent’s environment while localizing, or tracking that same agent’s pose in tandem. It is among the most challenging and fundamental tasks in computer vision, with applications ranging from augmented reality to robotic navigation. With the increasing capability and ubiquity of mobile computers such as cell phones, portable 3D SLAM systems are becoming feasible for widespread use. The Microsoft Hololens, Google Project Tango, and other 3D aware devices are modern day examples of the potential of SLAM and the challenges it has yet ...


Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held Dec 2016

Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held

Electronic Thesis and Dissertation Repository

Efficient and accurate tomographic image reconstruction has been an intensive topic of research due to the increasing everyday usage in areas such as radiology, biology, and materials science. Computed tomography (CT) scans are used to analyze internal structures through capture of x-ray images. Cone-beam CT scans project a cone-shaped x-ray to capture 2D image data from a single focal point, rotating around the object. CT scans are prone to multiple artifacts, including motion blur, streaks, and pixel irregularities, therefore must be run through image reconstruction software to reduce visual artifacts. The most common algorithm used is the Feldkamp, Davis, and ...


Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey Dec 2016

Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey

Masters Theses

In this thesis we designed, prototyped, and constructed a printed circuit board for real-time, low size, weight, and power (SWaP) HDMI video processing and developed a general purpose library of image processing functions for FPGAs.

The printed circuit board is a baseboard for a Xilinx Zynq based system-on-module (SoM). The board provides power, HDMI input, and HDMI output to the SoM and enables low-SWaP, high-resolution, real-time video processing.

The image processing library for FPGAs is designed for high performance and high reusability. These objectives are achieved by utilizing the Chisel hardware construction language to create parameterized modules that construct low-level ...


A Low Cost Timing Generation Unit, Christopher Vochoska Jun 2016

A Low Cost Timing Generation Unit, Christopher Vochoska

Computer Engineering

No abstract provided.


Software Defined Multi-Spectral Imaging For Arctic Sensor Networks, Sam B. Siewert, Matthew Demi Vis, Ryan Claus, Vivek Angoth, Karthikeyan Mani, Kenrick Mock, Surjith B. Singh, Saurav Srivistava, Chris Wagner Apr 2016

Software Defined Multi-Spectral Imaging For Arctic Sensor Networks, Sam B. Siewert, Matthew Demi Vis, Ryan Claus, Vivek Angoth, Karthikeyan Mani, Kenrick Mock, Surjith B. Singh, Saurav Srivistava, Chris Wagner

Publications

Availability of off-the-shelf infrared sensors combined with high definition visible cameras has made possible the construction of a Software Defined Multi-Spectral Imager (SDMSI) combining long-wave, near-infrared and visible imaging. The SDMSI requires a real-time embedded processor to fuse images and to create real-time depth maps for opportunistic uplink in sensor networks. Researchers at Embry Riddle Aeronautical University working with University of Alaska Anchorage at the Arctic Domain Awareness Center and the University of Colorado Boulder have built several versions of a low-cost drop-in-place SDMSI to test alternatives for power efficient image fusion. The SDMSI is intended for use in field ...


Energy Reduction Through Voltage Scaling And Lightweight Checking, Edin Kadric Jan 2016

Energy Reduction Through Voltage Scaling And Lightweight Checking, Edin Kadric

Publicly Accessible Penn Dissertations

As the semiconductor roadmap reaches smaller feature sizes and the end of Dennard Scaling, design goals change, and managing the power envelope often dominates delay minimization. Voltage scaling remains a powerful tool to reduce energy. We find that it results in about 60% geomean energy reduction on top of other common low-energy optimizations with 22nm CMOS technology. However, when voltage is reduced, it becomes easier for noise and particle strikes to upset a node, potentially causing Silent Data Corruption (SDC). The 60% energy reduction, therefore, comes with a significant drop in reliability. Duplication with checking and triple-modular redundancy are traditional ...


Computing Spmv On Fpgas, Kevin Rice Townsend Jan 2016

Computing Spmv On Fpgas, Kevin Rice Townsend

Graduate Theses and Dissertations

There are hundreds of papers on accelerating sparse matrix vector multiplication (SpMV), however, only a handful target FPGAs. Some claim that FPGAs inherently perform inferiorly to CPUs and GPUs. FPGAs do perform inferiorly for some applications like matrix-matrix multiplication and matrix-vector multiplication. CPUs and GPUs have too much memory bandwidth and too much floating point computation power for FPGAs to compete. However, the low computations to memory operations ratio and irregular memory access of SpMV trips up both CPUs and GPUs. We see this as a leveling of the playing field for FPGAs.

Our implementation focuses on three pillars: matrix ...


Using Reconfigurable Computing Technology To Accelerate Matrix Decomposition And Applications, Xinying Wang Jan 2016

Using Reconfigurable Computing Technology To Accelerate Matrix Decomposition And Applications, Xinying Wang

Graduate Theses and Dissertations

Matrix decomposition plays an increasingly significant role in many scientific and engineering applications. Among numerous techniques, Singular Value Decomposition (SVD) and Eigenvalue Decomposition (EVD) are widely used as factorization tools to perform Principal Component Analysis for dimensionality reduction and pattern recognition in image processing, text mining and wireless communications, while QR Decomposition (QRD) and sparse LU Decomposition (LUD) are employed to solve the dense or sparse linear system of equations in bioinformatics, power system and computer vision. Matrix decompositions are computationally expensive and their sequential implementations often fail to meet the requirements of many time-sensitive applications.

The emergence of reconfigurable ...


Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed Dec 2015

Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed

Master's Theses

Persons of visual impairment make up a growing segment of modern society. To cater to the special needs of these individuals, society ought to consider the design of special constructs to enable them to fulfill their daily necessities. This research proposes a new method for text extraction from indoor signage that will help persons of visual impairment maneuver in unfamiliar indoor environments, thus enhancing their independence and quality of life.

In this thesis, images are acquired through a video camera mounted on glasses of the walking person. Frames are then extracted and used in an integrated framework that applies Maximally ...


A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader Dec 2015

A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader

Master's Theses

Due to modern DNA sequencing technologies vast amount of short DNA sequences known as short-reads is generated. Biologists need to be able to align the short-reads to a reference genome to be able to make scientific use of the data. Fast and accurate short-read aligner programs are needed to keep up with the pace at which this data is generated. Field Programmable Gate Arrays have been widely used to accelerate many data-intensive bioinformatics applications.

Burrows-Wheeler Transform has been used in the theory of string matching which has led to the development of many short-read alignment programs. This thesis presents a ...


An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija Sep 2015

An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija

Master's Theses and Project Reports

Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm ...


Towards Real-Time, On-Board, Hardware-Supported Sensor And Software Health Management For Unmanned Aerial Systems, Johann M. Schumann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, Corey Ippolito Jun 2015

Towards Real-Time, On-Board, Hardware-Supported Sensor And Software Health Management For Unmanned Aerial Systems, Johann M. Schumann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, Corey Ippolito

Ole J Mengshoel

For unmanned aerial systems (UAS) to be successfully deployed and integrated within the national airspace, it is imperative that they possess the capability to effectively complete their missions without compromising the safety of other aircraft, as well as persons and property on the ground. This necessity creates a natural requirement for UAS that can respond to uncertain environmental conditions and emergent failures in real-time, with robustness and resilience close enough to those of manned systems. We introduce a system that meets this requirement with the design of a real-time onboard system health management (SHM) capability to continuously monitor sensors, software ...


Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty Jan 2015

Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty

Masters Theses

Internet plays a crucial part in today's world. Be it personal communication, business transactions or social networking, internet is used everywhere and hence the speed of the communication infrastructure plays an important role. As the number of users increase the network usage increases i.e., the network data rates ramped up from a few Mb/s to Gb/s in less than a decade. Hence the network infrastructure needed a major upgrade to be able to support such high data rates. Technological advancements have enabled the communication links like optical fibres to support these high bandwidths, but the processing ...


Design Exploration Of Hardware Accelerators For Mitigating The Effects Of Computational Delay On Digital Control Loops, Sudhanshu Prasad Vyas Jan 2015

Design Exploration Of Hardware Accelerators For Mitigating The Effects Of Computational Delay On Digital Control Loops, Sudhanshu Prasad Vyas

Graduate Theses and Dissertations

The field of modern control theory and the systems used to implement these controllers have developed rapidly and mostly exclusive of each other over the last 50 years. Digital control systems are traditionally designed assuming constant sensor sampling-rates and consistent processor response-times, with their implementation platform unaccounted for. Concurrently, embedded systems engineers focus on maximizing resource utilization by sharing processors amongst control and non-control tasks, causing unintended interactions. The result of this isolation between the two fields is that computing mechanisms meant to improve average CPU throughput, such as cache, interrupts, and task scheduling by operating systems, are contributing to ...


Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding Dec 2014

Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding

Theses and Dissertations

Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MPSoC) is an alternative way to balance the flexibility, the productivity, and the performance. However, without appropriate programming model it is still a challenge to achieve parallelism on a hybrid (MPSoC) with with both general-purpose processors and dedicated accelerators. Besides, increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing with emerging storage technologies is an alternative to enable the optimization ...


Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski Oct 2014

Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski

Andrew J. Kornecki

This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented.