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FPGA

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Full-Text Articles in Computer Engineering

Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris Jan 2019

Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris

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In recent decades, field programmable gate arrays (FPGAs) have evolved beyond simple, expensive computational components with minimal computing power to complex, inexpensive computational engines. Today, FPGAs can perform algorithmically complex problems with improved performance compared to sequential CPUs by taking advantage of parallelization. This concept can be readily applied to the computationally dense field of image manipulation and analysis. Processed on a standard CPU, image manipulation suffers with large image sets processed by highly sequential algorithms, but by carefully adhering to data dependencies, parallelized FPGA functions or kernels offer the possibility of significant improvement through threaded CPU functions. This thesis …


Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku Jan 2019

Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku

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System on Chip (SoC) is the backbone component of the electronics industry nowadays. ASIC and FPGA-based SoCs are the two most popular methods of manufacturing SoCs. However, both ASIC and FPGA industries are plagued with risks of counterfeits due to the limitations in Security, Accountability, Complexity, and Governance of their supply chain management. As a result, the current practices of these microelectronics supply chain suffer from performance and efficiency bottlenecks. In this research, we are incorporating blockchain technology into the FPGA and ASIC microelectronic supply chain to help mitigate the risk of counterfeit microelectronics through a secure and decentralized solution …


A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang Jan 2006

A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang

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Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an …