Low Cost Dynamic Architecture Adaptation Schemes For Drowsy Cache Management, Nitin Prakash

Masters Theses 1911 - February 2014

Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost dynamic architecture adaptation scheme to save leakage power in caches. This design uses voltage scaling to implement drowsy caches. The importance of a dynamic scheme for managing drowsy caches, arises from the fact that not only does cache behavior change from one application to the next, but also during different phases of execution within the same application. We discuss various implementations of our scheme that provide a tradeoff between granularity of control and design complexity. …

Activity Intent Recognition Of The Torso Based On Surface Electromyography And Inertial Measurement Units, Zhe Zhang

Masters Theses 1911 - February 2014

This thesis presents an activity mode intent recognition approach for safe, robust and reliable control of powered backbone exoskeleton. The thesis presents the background and a concept for a powered backbone exoskeleton that would work in parallel with a user. The necessary prerequisites for the thesis are presented, including the collection and processing of surface electromyography signals and inertial sensor data to recognize the user’s activity. The development of activity mode intent recognizer was described based on decision tree classification in order to leverage its computational efficiency. The intent recognizer is a high-level supervisory controller that belongs to a three-level …

A Dynamic Reconfiguration Framework To Maximize Performance/Power In Asymmetric Multicore Processors, Arunachalam Annamalai

Masters Theses 1911 - February 2014

Recent trends in technology scaling have shifted the processing paradigm to multicores. Depending on the characteristics of the cores, the multicores can be either symmetric or asymmetric. Prior research has shown that Asymmetric Multicore Processors (AMPs) outperform their symmetric (SMP) counterparts within a given resource and power budget. But, due to the heterogeneity in core-types and time-varying workload behavior, thread-to-core assignment is always a challenge in AMPs. As the computational requirements vary significantly across different applications and with time, there is a need to dynamically allocate appropriate computational resources on demand to suit the applications’ current needs, in order to …

Online Nbti Wear-Out Estimation, Mehernosh H. Dabhoiwala

Masters Theses 1911 - February 2014

CMOS feature size scaling has been a source of dramatic performance gains, but it has come at a cost of on-chip wear-out. Negative Bias Temperature Instability (NBTI) is one of the main on-chip wear-out problems which questions the reliability of a chip. To check the accuracy of Reaction-Diffusion (RD) model, this work first proposes to compare the NBTI wear-out data from the RD wear-out model and the reliability simulator - Ultrasim RelXpert, by monitoring the activity of the register file on a Leon3 processor. The simulator wear-out data obtained is considered to be the baseline data and is used to …

Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman

Masters Theses 1911 - February 2014

Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much faster and much more robust protocol than its predecessor, ATA (also referred to as Parallel ATA or IDE). Many hardware designs, including those using Field-Programmable Gate Arrays (FPGAs), have a need for a long-term storage solution, and a hard drive would be ideal. One such design is the high-speed Data Acquisition System (DAS) created for the NASA Surface Water and Ocean Topography mission. This system utilizes a Xilinx Virtex-4 FPGA. Although the DAS includes a SATA …

N3asics: Designing Nanofabrics With Fine-Grained Cmos Integration, Pavan Panchapakeshan

Masters Theses 1911 - February 2014

Nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. These fabrics employ unconventional manufacturing techniques like Nano-imprint lithography or Super-lattice Nanowire Pattern Transfer to produce ultra-dense nano-structures. However, one key challenge that has received limited attention is the interfacing of unconventional/self-assembly based approaches with conventional CMOS manufacturing to build integrated systems.

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules to build a reliable nanowire-CMOS 3-D integrated fabric called N³ASICs with no new manufacturing constraints. In N³ASICs …

A Study Of The Impact Of Computational Delays In Missile Interception Systems, Ye Xu

Masters Theses 1911 - February 2014

Most publications discussing missile interception systems assume a zero computer response time. This thesis studies the impact of computer response time on single-missile single-target and multiple- missile multiple-target systems. Simulation results for the final miss distance as the computer response time increases are presented. A simple online cooperative adjustment model for multiple-missile multiple-target system is created for the purpose of studying the computer delay effect.

Scheduling Heuristics For Maximizing The Output Quality Of Iris Task Graphs In Multiprocessor Environment With Time And Energy Bounds, Rajeswaran Chockalingapuram Ravindran

Masters Theses 1911 - February 2014

Embedded real time applications are often subject to time and energy constraints. Real time applications are usually characterized by logically separable set of tasks with precedence constraints. The computational effort behind each of the task in the system is responsible for a physical functionality of the embedded system. In this work we mainly define theoretical models for relating the quality of the physical func- tionality to the computational load of the tasks and develop optimization problems to maximize the quality of the system subject to various constraints like time and energy. Specifically, the novelties in this work are three fold. …

Techniques For Detection Of Malicious Packet Drops In Networks, Vikram R. Desai

Masters Theses 1911 - February 2014

The introduction of programmability and dynamic protocol deployment in routers, there would be an increase in the potential vulnerabilities and attacks . The next- generation Internet promises to provide a fundamental shift in the underlying architecture to support dynamic deployment of network protocols. In this thesis, we consider the problem of detecting malicious packet drops in routers. Specifically, we focus on an attack scenario, where a router selectively drops packets destined for another node. Detecting such an attack is challenging since it requires differentiating malicious packet drops from congestion-based packet losses. We propose a controller- based malicious packet detection technique …

Heterogeneous Graphene Nanoribbon-Cmos Multi-State Volatile Random Access Memory Fabric, Santosh Khasanvis

Masters Theses 1911 - February 2014

CMOS SRAM area scaling is slowing down due to several challenges faced by transistors at nanoscale such as increased leakage. This calls for new concepts and technologies to overcome CMOS scaling limitations. In this thesis, we propose a multi-state memory to store multiple bits in a single cell, enabled by graphene and graphene nanoribbon crossbar devices (xGNR). This could provide a new dimension for scaling. We present a new multi-state volatile memory fabric called Graphene Nanoribbon Tunneling Random Access Memory (GNTRAM) featuring a heterogeneous integration between graphene and CMOS. A latch based on the xGNR devices is used as the …

Simulating A Universal Geocast Scheme For Vehicular Ad Hoc Networks, Benjamin L. Bovee

Masters Theses 1911 - February 2014

Recently a number of communications schemes have been proposed for Vehicular Ad hoc Networks (VANETs). One of these, the Universal Geocast Scheme (UGS) proposed by Hossein Pishro-Nik and Mohammad Nekoui, provides for a diverse variety of VANET-specific characteristics such as time-varying topology, protocol variation based on road congestion, and support for non line-of-sight communication. In this research, the UGS protocol is extended to consider inter-vehicle multi-hop connections in intersections with surrounding obstructions along with single-hop communications in an open road scenario. Since UGS is a probabilistic, repetition-based scheme, it supports the capacity-delay tradeoffs crucial for periodic safety message exchange. The …

Addressing/Exploiting Transceiver Imperfections In Wireless Communication Systems, Lihao Wang

Masters Theses 1911 - February 2014

This thesis consists of two research projects on wireless communication systems. In the first project, we propose a fast inphase and quadrature (I/Q) imbalance compensation technique for the analog quadrature modulators in direct conversion transmitters. The method needs no training sequence, no extra background data gathering process and no prior perfect knowledge of the envelope detector characteristics. In contrast to previous approaches, it uses points from both the linear and predictable nonlinear regions of the envelope detector to hasten convergence. We provide a least mean square (LMS) version and demonstrate that the quadrature modulator compensator converges.

In the second project, …

A Real Time Web Based Electronic Triage, Resource Allocation And Hospital Dispatch System For Emergency Response, Venkata Srihari Inampudi

Masters Theses 1911 - February 2014

Disasters are characterized by large numbers of victims and required resources, overwhelming the available resources. Disaster response involves various entities like Incident Commanders, dispatch centers, emergency operations centers, area command and hospitals. An effective emergency response system should facilitate coordination between these various entities. Victim triage, emergency resource allocation and victim dispatch to hospitals form an important part of an emergency response system. In this present research effort, an emergency response system with the aforementioned components is developed.

Triage is the process of prioritizing mass casualty victims based on severity of injuries. The system presented in this thesis is a …

Parallel Mesh Adaptation And Graph Analysis Using Graphics Processing Units, Timothy P. Mcguiness

Masters Theses 1911 - February 2014

In the field of Computational Fluid Dynamics, several types of mesh adaptation strategies are used to enhance a mesh’s quality, thereby improving simulation speed and accuracy. Mesh smoothing (r-refinement) is a simple and effective technique, where nodes are repositioned to increase or decrease local mesh resolution. Mesh partitioning divides a mesh into sections, for use on distributed-memory parallel machines. As a more abstract form of modeling, graph theory can be used to simulate many real-world problems, and has applications in the fields of computer science, sociology, engineering and transportation, to name a few. One of the more important graph analysis …

Leveraging Multi-Radio Communication For Mobile Wireless Sensor Networks, Jeremy J. Gummeson

Masters Theses 1911 - February 2014

An important challenge in mobile sensor networks is to enable energy-efficient communication over a diversity of distances while being robust to wireless effects caused by node mobility. In this thesis, we argue that the pairing of two complementary radios with heterogeneous range characteristics enables greater range and interference diversity at lower energy cost than a single radio. We make three contributions towards the design of such multi-radio mobile sensor systems. First, we present the design of a novel reinforcement learning-based link layer algorithm that continually learns channel characteristics and dynamically decides when to switch between radios. Second, we describe a …

Hardware Implementation Of Queue Length Based Pacing On Netfpga, Abhishek Dwaraki

Masters Theses 1911 - February 2014

Optical packet switching networks are the foundation for next generation high speed Internet and are fast becoming the norm rather than an option. When such high speed optical networks are taken into account, one of the key considerations is packet buffering. The importance of packet buffering plays an even bigger role in optical networks because of the physical and technological constraints on the buffer sizes that can be implemented. Existing protocols, in many real world scenarios do not perform well in such networks. To eliminate such scenarios where there is a high possibility of packet loss, we use packet pacing. …

A Real Time Indoor Navigation And Monitoring System For Firefighters And Visually Impaired, Siddhesh R. Gandhi

Masters Theses 1911 - February 2014

ABSTRACT

A REAL TIME INDOOR NAVIGATION AND MONITORING SYSTEM FOR FIREFIGHTERS AND VISUALLY IMPAIRED

MAY 2011

SIDDHESH RAJAN GANDHI

M.S. E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERST

Directed by: Professor Aura Ganz

There has been a widespread growth of technology in almost every facet of day to day life. But there are still important application areas in which technology advancements have not been implemented in a cost effective and user friendly manner. Such applications which we will address in this proposal include: 1) indoor localization and navigation of firefighters during rescue operations and 2) indoor localization and navigation for the blind and …

Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj

Masters Theses 1911 - February 2014

Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance …

Evaluating A New Mac For Current And Next Generation Rfid, Serge Zhilyaev

Masters Theses 1911 - February 2014

We evaluate SQUASH, a new MAC for RFID, in hardware and software. A smaller hardware design for SQUASH is proposed which also reduces latency. Area and latency in hardware are reduced further with a new variant we call permuted SQUASH. We explore SQUASH on embedded microprocessors and propose a method to choose the optimal partial product ordering to reduce latency.

Web-Dinar: Web Based Diagnosis Of Network And Application Resources In Disaster Response Systems, Kartik Deshpande

Masters Theses 1911 - February 2014

Disaster management and emergency response mechanisms are coming of age post 9/11. Paper based triaging and evacuation is slowly being replaced with much advanced mechanisms using remote clients (Laptops, Thin clients, PDAs), RFiDs etc. This reflects a modern trend to deploy Information Technology (IT) in disaster management. IT elements provide a great a deal of flexibility and seamlessness in the communication of information. The information flowing is so critical that, loss of data is not at all acceptable. Loss of data would mean loss of critical medical information portraying the disaster scenario. This would amount to a wrong picture being …

Application Specific Customization And Scalability Of Soft Multiprocessors, Deepak C. Unnikrishnan

Masters Theses 1911 - February 2014

Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After …

Indexing Trace, Zachary E. Smith

Masters Theses 1911 - February 2014

This thesis aims to critically examine the relationship of digital technology and the modern art gallery in order to find the possible role of art galleries in the future. The integration of technology and the modern art gallery can change the way people experience art in built space.

In order to examine this, certain questions needed to be asked. The most important of these questions is authenticity and originality in a digital art gallery. What if, in order for the notion of originality to exist, it needs the notion of the copy; a kind of parasite. What if we don’t …

Implementation Of Data Path Credentials For High-Performance Capabilities-Based Networks, Kamlesh T. Vasudevan

Masters Theses 1911 - February 2014

Capabilities-based networks present a fundamental shift in the security design of network architectures. Instead of permitting the transmission of packets from any source to any destination, routers deny forwarding by default. For a successful transmission, packets need to positively identify themselves and their permissions to the router. A major challenge for a high performance implementation of such a network is an efficient design of the credentials that are carried in the packet and the verification procedure on the router. A network protocol that implements data path credentials based on Bloom filters is presented in this thesis. Our prototype implementation shows …

A Hardware Framework For Yield And Reliability Enhancement In Chip Multiprocessors, Abhisek Pan

Masters Theses 1911 - February 2014

Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. Today an increasing number of hardware failures are attributed to device reliability problems that cause partial system failure or shutdown. Also maintaining an acceptable manufacturing yield is seen as challenge because of smaller feature sizes, process variation, and reduced headroom for burn-in tests. In this project we investigate a hardware-based scheme for improving yield and reliability of a homogeneous chip multiprocessor (CMP). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multi-core system to keep the system operational in …

Implementation Of Network Services Supporting Multi-Party Policies, Santosh C. Proddatoori

Masters Theses 1911 - February 2014

Next-generation network architectures support complex services in the data-path of routers. A key challenge is the integration of multiple policy constraints from senders, receivers, and network providers when using such services. We introduce a multi-party service specification framework based on our “service socket” API. We illustrate the operation of this approach in an IPTV scenario that uses a video transcoding service implemented on a Cisco ISR platform.