Open Access. Powered by Scholars. Published by Universities.®
- Keyword
-
- Hardware Security (3)
- ASIC (2)
- FPGA (2)
- Hardware security (2)
- Obfuscation (2)
-
- Physically Unclonable Functions (2)
- Reliability (2)
- SRAM (2)
- 3D Architecture (1)
- 3D Circuits (1)
- 3D IC (1)
- 3D Memory (1)
- ALU (1)
- Camouflaging (1)
- Computer Algebra (1)
- Crosstalk-based attacks (1)
- Device-to-system Simulation (1)
- Divider verification (1)
- Dynamic Precision (1)
- Embedded systems (1)
- Fault-injection attacks (1)
- Floating-Point (1)
- Formal Verification (1)
- Gate-level (1)
- Groebner Basis (1)
- High-resolution (1)
- Integrated Circuits (1)
- Iterative refinement (1)
- Low-cost (1)
- Machine Learning (1)
Articles 1 - 13 of 13
Full-Text Articles in Computer Engineering
On Improving Robustness Of Hardware Security Primitives And Resistance To Reverse Engineering Attacks, Vinay C. Patil
On Improving Robustness Of Hardware Security Primitives And Resistance To Reverse Engineering Attacks, Vinay C. Patil
Doctoral Dissertations
The continued growth of information technology (IT) industry and proliferation of interconnected devices has aggravated the problem of ensuring security and necessitated the need for novel, robust solutions. Physically unclonable functions (PUFs) have emerged as promising secure hardware primitives that can utilize the disorder introduced during manufacturing process to generate unique keys. They can be utilized as \textit{lightweight} roots-of-trust for use in authentication and key generation systems. Unlike insecure non-volatile memory (NVM) based key storage systems, PUFs provide an advantage -- no party, including the manufacturer, should be able to replicate the physical disorder and thus, effectively clone the PUF. …
Addressing Security Challenges In Embedded Systems And Multi-Tenant Fpgas, Georgios Provelengios
Addressing Security Challenges In Embedded Systems And Multi-Tenant Fpgas, Georgios Provelengios
Doctoral Dissertations
Embedded systems and field-programmable gate arrays (FPGAs) have become crucial parts of the infrastructure that supports our modern technological world. Given the multitude of threats that are present, the need for secure computing systems is undeniably greater than ever. Embedded systems and FPGAs are governed by characteristics that create unique security challenges and vulnerabilities. Despite their array of uses, embedded systems are often built with modest microprocessors that do not support the conventional security solutions used by workstations, such as virus scanners. In the first part of this dissertation, a microprocessor defense mechanism that uses a hardware monitor to protect …
Formal Verification Of Divider And Square-Root Arithmetic Circuits Using Computer Algebra Methods, Atif Yasin
Formal Verification Of Divider And Square-Root Arithmetic Circuits Using Computer Algebra Methods, Atif Yasin
Doctoral Dissertations
A considerable progress has been made in recent years in verification of arithmetic circuits such as multipliers, fused multiply-adders, multiply-accumulate, and other components of arithmetic datapaths, both in integer and finite field domain. However, the verification of hardware dividers and square-root functions have received only a limited attention from the verification community, with a notable exception for theorem provers and other inductive, non-automated systems. Division, square root, and transcendental functions are all tied to the basic Intel architecture and proving correctness of such algorithms is of grave importance. Although belonging to the same iterative-subtract class of architectures, they widely differ …
Design Of Hardware With Quantifiable Security Against Reverse Engineering, Shahrzad Keshavarz
Design Of Hardware With Quantifiable Security Against Reverse Engineering, Shahrzad Keshavarz
Doctoral Dissertations
Semiconductors are a 412 billion dollar industry and integrated circuits take on important roles in human life, from everyday use in smart-devices to critical applications like healthcare and aviation. Saving today's hardware systems from attackers can be a huge concern considering the budget spent on designing these chips and the sensitive information they may contain. In particular, after fabrication, the chip can be subject to a malicious reverse engineer that tries to invasively figure out the function of the chip or other sensitive data. Subsequent to an attack, a system can be subject to cloning, counterfeiting, or IP theft. This …
Time-Difference Circuits: Methodology, Design, And Digital Realization, Shuo Li
Time-Difference Circuits: Methodology, Design, And Digital Realization, Shuo Li
Doctoral Dissertations
This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: …
Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, Jiajun Shi
Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, Jiajun Shi
Doctoral Dissertations
2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is …
Intrinsic Functions For Securing Cmos Computation: Variability, Modeling And Noise Sensitivity, Xiaolin Xu
Intrinsic Functions For Securing Cmos Computation: Variability, Modeling And Noise Sensitivity, Xiaolin Xu
Doctoral Dissertations
A basic premise behind modern secure computation is the demand for lightweight cryptographic primitives, like identifier or key generator. From a circuit perspective, the development of cryptographic modules has also been driven by the aggressive scalability of complementary metal-oxide-semiconductor (CMOS) technology. While advancing into nano-meter regime, one significant characteristic of today's CMOS design is the random nature of process variability, which limits the nominal circuit design. With the continuous scaling of CMOS technology, instead of mitigating the physical variability, leveraging such properties becomes a promising way. One of the famous products adhering to this double-edged sword philosophy is the Physically …
Arithmetic Logic Unit Architectures With Dynamically Defined Precision, Getao Liang
Arithmetic Logic Unit Architectures With Dynamically Defined Precision, Getao Liang
Doctoral Dissertations
Modern central processing units (CPUs) employ arithmetic logic units (ALUs) that support statically defined precisions, often adhering to industry standards. Although CPU manufacturers highly optimize their ALUs, industry standard precisions embody accuracy and performance compromises for general purpose deployment. Hence, optimizing ALU precision holds great potential for improving speed and energy efficiency. Previous research on multiple precision ALUs focused on predefined, static precisions. Little previous work addressed ALU architectures with customized, dynamically defined precision. This dissertation presents approaches for developing dynamic precision ALU architectures for both fixed-point and floating-point to enable better performance, energy efficiency, and numeric accuracy. These new …
Skybridge: A New Nanoscale 3-D Computing Framework For Future Integrated Circuits, Mostafizur Rahman
Skybridge: A New Nanoscale 3-D Computing Framework For Future Integrated Circuits, Mostafizur Rahman
Doctoral Dissertations
Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We …
Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar
Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar
Doctoral Dissertations
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of "hardware Trojans" inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart …
Managing And Leveraging Variations And Noise In Nanometer Cmos, Vikram B. Suresh
Managing And Leveraging Variations And Noise In Nanometer Cmos, Vikram B. Suresh
Doctoral Dissertations
Advanced CMOS technologies have enabled high density designs at the cost of complex fabrication process. Variation in oxide thickness and Random Dopant Fluctuation (RDF) lead to variation in transistor threshold voltage Vth. Current photo-lithography process used for printing decreasing critical dimensions result in variation in transistor channel length and width. A related challenge in nanometer CMOS is that of on-chip random noise. With decreasing threshold voltage and operating voltage; and increasing operating temperature, CMOS devices are more sensitive to random on-chip noise in advanced technologies. In this thesis, we explore novel circuit techniques to manage the impact of …
Parallel Multi-Core Verilog Hdl Simulation, Tariq B. Ahmad
Parallel Multi-Core Verilog Hdl Simulation, Tariq B. Ahmad
Doctoral Dissertations
In the era of multi-core computing, the push for creating true parallel applications that can run on individual CPUs is on the rise. Application of parallel discrete event simulation (PDES) to hardware design verification looks promising, given the complexity of today’s hardware designs. Unfortunately, the challenges imposed by lack of inherent parallelism, suboptimal design partitioning, synchronization and communication overhead, and load balancing, render this approach largely ineffective. This thesis presents three techniques for accelerating simulation at three levels of abstraction namely, RTL, functional gate-level (zero-delay) and gate-level timing. We review contemporary solutions and then propose new ways of speeding up …
Air: Adaptive Dynamic Precision Iterative Refinement, Jun Kyu Lee
Air: Adaptive Dynamic Precision Iterative Refinement, Jun Kyu Lee
Doctoral Dissertations
In high performance computing, applications often require very accurate solutions while minimizing runtimes and power consumption. Improving the ratio of the number of logic gates implementing floating point arithmetic operations to the total number of logic gates enables greater efficiency, potentially with higher performance and lower power consumption. Software executing on the fixed hardware in Von-Neuman architectures faces limitations on improving this ratio, since processors require extensive supporting logic to fetch and decode instructions while employing arithmetic units with statically defined precision. This dissertation explores novel approaches to improve computing architectures for linear system applications not only by designing application-specific …