Computer Engineering Commons^™

Floating-Point Divide And Square Root For Efficient Fpga Implementation Of Image And Signal Processing Algorithms, Xiaojun Wang, Miriam Leeser

Miriam Leeser

Division and square root are important operations in any high performance signal processing applications. We have implemented floating point division and square root based on Taylor series for the variable precision floating point library developed at the Reconfigurable Computing Laboratory at Northeastern. Our result shows that they are very well suited to FPGA implementations, and lead to a good tradeoff of area and latency. We implemented a floating-point K-means clustering algorithm and applied it to multispectral satellite images. The mean update is moved from host to FPGA hardware with the new fp_div module to reduce the communication between host and …