Computer Engineering Commons^™

Analysis And Optimization Of A Banyan Based Atm Switch By Simulations, Syed Sohel Hussain

Dissertations and Theses

Asynchronous Transfer Mode (ATM) is proposed technology to create a broadband (high speed) packet switching network capable of transporting wide variety of services including voice, video and data in an integrated manner. The main concern in designing the switching fabrics used in this technology are speed, throughput, delay and variance of delay. We analyze the performance by simulations of ATM switch based on Banyan network in the uniform traffic condition.

We compare the analytical results obtained from three-state model Yan and Jenq to the simulation results. Based on observation of simulation results, we propose non-blocking first stage (NBFS) to increase …

Atomic Broadcast In Heterogeneous Distributed Systems, Osman Zeineldine

Computer Science Theses & Dissertations

Communication services have long been recognized as possessing a dominant effect on both performance and robustness of distributed systems. Distributed applications rely on a multitude of protocols for the support of these services. Of crucial importance are multicast protocols. Reliable multicast protocols enhance the efficiency and robustness of distributed systems. Numerous reliable multicast protocols have been proposed, each differing in the set of assumptions adopted, especially for the communication network. These assumptions make each protocol suitable for a specific environment. The presence of different distributed applications that run on different LANs and single distributed applications that span different LANs mandate …

Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford

Theses and Dissertations

This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.

Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp

Theses and Dissertations

Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …

Ignoring Interprocessor Communication During Scheduling, Chintamani M. Patwardhan

Dissertations and Theses

The goal of parallel processing is to achieve high speed computing by partitioning a program into concurrent parts, assigning them in an efficient way to the available processors, scheduling the program and then executing the concurrent parts simultaneously. In the past researchers have combined the allocation of tasks in a program and scheduling of those tasks into one operation. We define scheduling as a process of efficiently assigning priorities to the already allocated tasks in a program. Assignment of priorities is important in cases when more than one task at a processor is ready for execution. Most heuristics for scheduling …

Parallel Architectures For Solving Combinatorial Problems Of Logic Design, Phuong Minh Ho

Dissertations and Theses

This thesis presents a new, practical approach to solve various NP-hard combinatorial problems of logic synthesis, logic programming, graph theory and related areas. A problem to be solved is polynomially time reduced to one of several generic combinatorial problems which can be expressed in the form of the Generalized Propositional Formula (GPF) : a Boolean product of clauses, where each clause is a sum of products of negated or non-negated literals.

Two Dimensional And Three Dimensional Path Planning In Robotics, Hyun Suk Kim

Dissertations and Theses

A methodology for 2D and 3D collision free path planning algorithm in a structured environment is presented. The isolated free convex areas are represented as a nodes in a graph, and a graph traversal strategy that dynamically allocates costs to graph path is used. Modification of the algorithm for small computational time and optimality is discussed. The 3D path planning is done in the three orthogonal two-dimensional projections of a 3D environment. Collision checking to increase the optimality for 3D paths is done in each of the three orthogonal two-dimensional subspaces.

Compiling Unit Clauses For The Warren Abstract Machine, George D. Herbert

UNF Graduate Theses and Dissertations

This thesis describes the design, development, and installation of a computer program which compiles unit clauses generated in a Prolog-based environment at Argonne National Laboratories into Warren Abstract Machine (WAM) code. The program enhances the capabilities of the environment by providing rapid unification and subsumption tests for the very significant class of unit clauses. This should improve performance substantially for large programs that generate and use many unit clauses.

Design And Applications Of A Graphics Package For The Hp1000 Computer., Hsiao-Chih George Lee

Electronic Theses and Dissertations

The objective of this thesis is to develop the FORTRAN subroutine PLOTER which is a general-purpose plotting tool to plot charts on a Hewlett Packard plotter. The programs RESP and INVLAP which can plot the frequency and time responses of system functions are modified to adopt the PLOTER subroutine and are stored of the HP1000-A900 minicomputer whose software, the GRAPHICS/1000, supports the graphics ability of PLOTER. This thesis describes the theories, functions, software techniques and operations of the PLOTER subroutine and the application programs RESP and the INVLAP. It also provides program listings and example plots.

Systems Reliability Using The Flow Graph, Kenneth Edward Farrier

Dissertations and Theses

The problem of calculating the reliability of a complex system of interacting elements is delineated to a linear system, no element of the system having a reliability distribution in terms of any other e1ement of the system, where only one path is taken through the system at a time. A precise definition is then developed to specify the reliability of the linear, single path at a time, system. A precise and concise generating function is found that effortlessly produces the reliability of the linear, single path at a time, system directly from the reliability flew graph of the system.