Computer Engineering Commons^™

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Design And Implementation Of A Low Cost And Portable Tactile Stimulator, Coşkun Kazma, Vecdi̇ Emre Levent, Merve Çardak, Ni̇zametti̇n Aydin

Turkish Journal of Electrical Engineering and Computer Sciences

When central nervous system has a problem, somatic area I and II respond to stimulation differently. Therefore, it is possible to identify some of the central nervous diseases when somatosensory on the fingertip is stimulated and responses are recorded and analyzed. We designed a system to stimulate the mechanoreceptors on fingertips. It is composed of a mechanical system for fingertip stimulation, an embedded controller, a control computer, and a software to control overall operation. During test, mechanoreceptors are stimulated according to the test protocols. Individuals' answers are recorded to be evaluated by the developed software. In this study, several design …

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett

Masters Theses

The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.

The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …

Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse

Masters Theses

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …

An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke

Graduate Theses and Dissertations

The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …

Trustworthy Systems And Protocols For The Internet Of Things, Arman Pouraghily

Doctoral Dissertations

Processor-based embedded systems are integrated into many aspects of everyday life such as industrial control, automotive systems, healthcare, the Internet of Things, etc. As Moore’s law progresses, these embedded systems have moved from simple microcontrollers to full-scale embedded computing systems with multiple processor cores and operating systems support. At the same time, the security of these devices has also become a key concern. Our main focus in this work is the security and privacy of the embedded systems used in IoT systems. In the first part of this work, we take a look at the security of embedded systems from …

Time-Difference Circuits: Methodology, Design, And Digital Realization, Shuo Li

Doctoral Dissertations

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: …

Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton

Theses and Dissertations

An Adaptive-Hybrid Redundancy (AHR) mitigation strategy is proposed to mitigate the effects of Single Event Upset (SEU) and Single Event Transient (SET) radiation effects. AHR is adaptive because it switches between Triple Modular Redundancy (TMR) and Temporal Software Redundancy (TSR). AHR is hybrid because it uses hardware and software redundancy. AHR is demonstrated to run faster than TSR and use less energy than TMR. Furthermore, AHR allows space vehicle designers, mission planners, and operators the flexibility to determine how much time is spent in TMR and TSR. TMR mode provides faster processing at the expense of greater energy usage. TSR …

Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally

Information Science Faculty Publications

One of the most important Internet of Things applications is the wireless body sensor network (WBSN), which can provide universal health care, disease prevention, and control. Due to large deployments of small scale smart sensors in WBSNs, security, and privacy guarantees (e.g., security and safety-critical data, sensitive private information) are becoming a challenging issue because these sensor nodes communicate using an open channel, i.e., Internet. We implement data integrity (to resist against malicious tampering) using the secure hash algorithm 3 (SHA-3) when smart sensors in WBSNs communicate with each other using the Internet. Due to the limited resources (i.e., storage, …

Highly Accurate And Sensitive Short Read Aligner, Mehmet Yağmur Gök, Sezer Gören Uğurdağ, Cem Ünsalan, Mahmut Şami̇l Sağiroğlu

Turkish Journal of Electrical Engineering and Computer Sciences

Next-generation sequencing generates large numbers of short reads from DNA. This makes it difficult to process and store. Therefore, efficient sequence alignment and mapping techniques are needed in bioinformatics. Alignment and mapping are the basic steps involved in genetic data analysis. The Smith-Waterman (SW) algorithm, a well-known dynamic programming algorithm, is often used for this purpose. In this work, we propose to utilize Phred quality scores in Gotoh's affine gap model to increase the accuracy and sensitivity of the SW algorithm. Hardware platforms such as FPGAs and GPUs are commonly used to solve computationally expensive problems. In this work, a …

General-Purpose Digital Filter Platform, Michael Cheng

Electrical Engineering

This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes a …

Modeling And Control Of A Permanent-Magnet Brushless Dc Motor Drive Using A Fractional Order Proportional-Integral-Derivative Controller, Swapnil Khubalkar, Anjali Junghare, Mohan Aware, Shantanu Das

Turkish Journal of Electrical Engineering and Computer Sciences

This paper deals with the speed control of a permanent-magnet brushless direct current (PMBLDC) motor. A fractional order PID (FOPID) controller is used in place of the conventional PID controller. The FOPID controller is a generalized form of the PID controller in which the order of integration and differentiation is any real number. It is shown that the proposed controller provides a powerful framework to control the PMBLDC motor. Parameters of the controller are found by using a novel dynamic particle swarm optimization (dPSO) method. The frequency domain pole-zero (p-z) interlacing method is used to approximate the fractional order operator. …

Automatic Arrhythmia Beat Detection: Algorithm, System, And Implementation, Wisnu Jatmiko, I Md. Agus Setiawan, Muhammad Ali Akbar, Muhammad Eka Suryana, Yulistiyan Wardhana, Muhammad Febrian Rachmadi

Makara Journal of Technology

Cardiac disease is one of the major causes of death in the world. Early diagnose of the symptoms depends on abnormality on heart beat pattern, known as Arrhythmia. A novel fuzzy neuro generalized learning vector quantization for automatic Arrhythmia heart beat classification is proposed. The algorithm is an extension from the GLVQ algorithm that employs a fuzzy logic concept as the discriminant function in order to develop a robust algorithm and improve the classification performance. The algorithm is tested against MIT-BIH arrhythmia database to measure the performance. Based on the experiment result, FN-GLVQ is able to increase the accuracy of …

High Dynamic Performance Of A Bldc Motor With A Front End Converter Using An Fpga Based Controller For Electric Vehicle Application, Praveen Yadav, Rajesh Poola, Khaja Najumudeen

Turkish Journal of Electrical Engineering and Computer Sciences

This paper focus on a novel operation of a brushless dc (BLDC) motor fed by a proportional integral (PI) controlled buck--boost converter supplemented with a battery to provide the required power to drive the BLDC motor. The operational characteristics of the proposed BLDC motor drive system for constant as well as step changes in dc link voltage of a front end converter controlled by a Xilinx System Generator (XSG) based PI controller for two quadrant operations are derived. Thus a field programmable gate array (FPGA) based PI controller manages the energy flow through the battery and the front end converter. …

Fpga Implementation Of A Hevc Deblocking Filter For Fast Processing Of Super High Resolution Applications, Awais Khan, Gulistan Raja

Turkish Journal of Electrical Engineering and Computer Sciences

This paper proposes the architecture of a deblocking filter (DBF) that removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). A parallel architecture for both normal and strong filtering modes of HEVC is proposed. Distributed memories and two data paths increase the parallelism and make the architecture more efficient. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real time to compute 4K UHD video at 30 fps by using 46.65 million clocks with total equivalent gate count of 46K. The maximum delay time for output to come after taking input for …

Implementation Of A Modified Svpwm-Based Three-Phase Inverter With Reduced Switches Using A Single Dc Source For A Grid-Connected Pv System, Venkatesan Mani, Rajeswari Ramachandran, Deverajan Nanjundappan

Turkish Journal of Electrical Engineering and Computer Sciences

No abstract provided.

An Alternative Carry-Save Arithmetic For New Generation Field Programmable Gate Arrays, Uğur Çi̇ni̇, Mustafa Aktan, Avni̇ Morgül

Turkish Journal of Electrical Engineering and Computer Sciences

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than …

Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed

Masters Theses

Persons of visual impairment make up a growing segment of modern society. To cater to the special needs of these individuals, society ought to consider the design of special constructs to enable them to fulfill their daily necessities. This research proposes a new method for text extraction from indoor signage that will help persons of visual impairment maneuver in unfamiliar indoor environments, thus enhancing their independence and quality of life.

In this thesis, images are acquired through a video camera mounted on glasses of the walking person. Frames are then extracted and used in an integrated framework that applies Maximally …

A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader

Masters Theses

Due to modern DNA sequencing technologies vast amount of short DNA sequences known as short-reads is generated. Biologists need to be able to align the short-reads to a reference genome to be able to make scientific use of the data. Fast and accurate short-read aligner programs are needed to keep up with the pace at which this data is generated. Field Programmable Gate Arrays have been widely used to accelerate many data-intensive bioinformatics applications.

Burrows-Wheeler Transform has been used in the theory of string matching which has led to the development of many short-read alignment programs. This thesis presents a …

An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija

Master's Theses

Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …

Designing And Implementing A Reliable Thermal Monitoring System Based On The 1-Wire Protocol On Fpga For A Leo Satellite, Reza Omidi Gosheblagh, Karim Mohammadi

Turkish Journal of Electrical Engineering and Computer Sciences

Thermal control and monitoring is one of the most important factors in the design of satellite systems. An appropriate thermal design should make sure that the satellite's sensitive components remain in their nominated range, even under the vacuum condition of outer space. To achieve this purpose, a reliable and stable monitoring system is required. This paper proposes a monitoring system based on the 1-wire protocol, which provides the reliability requirements in the sensor networking and bus controller sections. In the networking section, we outline some practical topologies and discuss on their complexity and reliability. Despite the fact that the point-to-point …

Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding

Graduate Theses and Dissertations

Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MPSoC) is an alternative way to balance the flexibility, the productivity, and the performance. However, without appropriate programming model it is still a challenge to achieve parallelism on a hybrid (MPSoC) with with both general-purpose processors and dedicated accelerators. Besides, increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing with emerging storage technologies is an alternative to enable the optimization …

Reconfigurable Technologies For Next Generation Internet And Cluster Computing, Deepak C. Unnikrishnan

Open Access Dissertations

Modern web applications are marked by distinct networking and computing characteristics. As applications evolve, they continue to operate over a large monolithic framework of networking and computing equipment built from general-purpose microprocessors and Application Specific Integrated Circuits (ASICs) that offers few architectural choices. This dissertation presents techniques to diversify the next-generation Internet infrastructure by integrating Field-programmable Gate Arrays (FPGAs), a class of reconfigurable integrated circuits, with general-purpose microprocessor-based techniques. Specifically, our solutions are demonstrated in the context of two applications - network virtualization and distributed cluster computing.

Network virtualization enables the physical network infrastructure to be shared among several …

Applied Hw/Sw Co-Design: Using The Kendall Tau Algorithm For Adaptive Pacing, Kenneth W. Chee

Master's Theses

Microcontrollers, the brains of embedded systems, have found their way into every aspect of our lives including medical devices such as pacemakers. Pacemakers provide life supporting functions to people therefore it is critical for these devices to meet their timing constraints. This thesis examines the use of hardware co-processing to accelerate the calculation time associated with the critical tasks of a pacemaker. In particular, we use an FPGA to accelerate a microcontroller’s calculation time of the Kendall Tau Rank Correlation Coefficient algorithm. The Kendall Tau Rank Correlation Coefficient is a statistical measure that determines the pacemaker’s voltage level for heart …

Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman

Masters Theses 1911 - February 2014

Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much faster and much more robust protocol than its predecessor, ATA (also referred to as Parallel ATA or IDE). Many hardware designs, including those using Field-Programmable Gate Arrays (FPGAs), have a need for a long-term storage solution, and a hard drive would be ideal. One such design is the high-speed Data Acquisition System (DAS) created for the NASA Surface Water and Ocean Topography mission. This system utilizes a Xilinx Virtex-4 FPGA. Although the DAS includes a SATA …

System Designs To Perform Bioinformatics Sequence Alignment, Çağlar Yilmaz, Mustafa Gök

Turkish Journal of Electrical Engineering and Computer Sciences

The emerging field of bioinformatics uses computing as a tool to understand biology. Biological data of organisms (nucleotide and amino acid sequences) are stored in databases that contain billions of records. In order to process the vast amount of data in a reasonable time, high-performance analysis systems are developed. The main operation shared by the analysis tools is the search for matching patterns between sequences of data (sequence alignment). In this paper, we present 2 systems that can perform pairwise and multiple sequence alignment operations. Through the optimized design methods, proposed systems achieve up to 3.6 times more performance compared …

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …

Design Of An Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture, Joshua R. Templin

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Processing power is a key technical challenge holding back the development of a high-performance software defined radio (SDR). Traditionally, SDR has utilized digital signal processors (DSPs), but increasingly complex algorithms, higher data rates, and multi-tasking needs have exceed the processing capabilities of modern DSPs. Reconfigurable computers, such as field-programmable gate arrays (FPGAs), are popular alternatives because of their performance gains over software for streaming data applications like SDR. However, FPGAs have not yet realized the ideal SDR because architectures have not fully utilized their partial reconfiguration (PR) capabilities to bring needed flexibility. A reconfigurable processor architecture is proposed that utilizes …