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Full-Text Articles in Computer Engineering
On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu
On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu
UNLV Theses, Dissertations, Professional Papers, and Capstones
High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.
Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
College of Engineering: Graduate Celebration Programs
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …
Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen
Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen
Electrical & Computer Engineering Faculty Research
We introduce the notion of free region of a node in a sensor network. Intuitively, a free region of a node is the connected set of points R in its neighborhood such that the connectivity of the network remains the same when the node is moved to any point in R. We characterize several properties of free regions and develop an efficient algorithm for computing them. We capture free region in terms of related notions called in-free region and out-free region. We present an O(n2) algorithm for constructing the free region of a node, where n is the number of …